xr16c2552ij Exar Corporation, xr16c2552ij Datasheet - Page 24

• Manufacturer Part Number: xr16c2552ij
• Description: 2.97v To 5.5v Dual Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
See MCR bit-7 and the baud rate table also.
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
AFR[7:3]: Reserved
All are initialized to logic 0.
4.12
4.13
Baud Rate = (Clock Frequency / 16) / Divisor
Logic 0 = No concurrent write (default).
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
Baud Rate Generator Registers (DLL and DLM) - Read/Write
Alternate Function Register (AFR) - Read/Write
B
IT
0
0
1
1
-2
B
IT
0
1
0
1
-1
24
MF# F
OP2# (default)
BAUDOUT#
Reserved
RXRDY#
UNCTION
xr
REV. 1.0.0