xr20v2172 Exar Corporation, xr20v2172 Datasheet
xr20v2172
Related parts for xr20v2172
xr20v2172 Summary of contents
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... Covered by U.S. Patent #5,649,122 OTE APPLICATIONS • Portable Appliances • Battery-Operated Devices • Cellular Data Devices • Factory Automation and Process Controls F 1. XR20V2172 B D IGURE LOCK IAGRAM C rys ffe ...
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... RTSB 5 RXB_SEL 6 RXB 7 TXB 8 N. N.C. DTRB 12 RIB 13 DSRB 14 XTAL1 15 GND 16 ORDERING INFORMATION ART UMBER XR20V2172IL64 64-pin QFN XR20V2172 64-pin QFN O T ACKAGE PERATING EMPERATURE -40°C to +85°C 2 REV. 1.0.0 48 N.C. 47 N.C. 46 N.C. 45 VCC 44 C2+ 43 C2- 42 TXDA DTRA 41 DSRA 40 RXDA 39 38 IRQ ...
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... RTS flow control, see EFR[6], MCR[1] and IER[6]. I UART Clear-to-Send. It can be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input has an internal pull-down resistor and can be left unconnected when not used. 3 XR20V2172 ESCRIPTION 2 C-bus interface is selected if this pin is 2 C-bus configura- ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER Pin Description 64-QFN N AME DTRA 12 DTRB 40 DSRA 14 DSRB 60 CDA 62 CDB 58 RIA 13 RIB Ancillary signals (CMOS/TTL Voltage Levels) 15 XTAL1 XTAL2 17 24 ACP 19 FAST 20 R_EN RXB_SEL 6 44 C2+ 43 C2- 51 C1+ 50 C1- ...
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... For RS-232 output voltage levels, ’LOW’ is any voltage < -5V and ’HIGH’ is any voltage > 5V YPE - No Connection. 5 XR20V2172 ESCRIPTION For CMOS/TTL Voltage levels, ’LOW’ ...
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... EIA RS-232F specifications. Additionally, the V2172 includes the ACP pin with which the user can shut down the charge pump for the RS-232 drivers when the V2172 is already in sleep mode. The XR20V2172 is a 3.3 to 5.5V device. The V2172 is fabricated with an advanced CMOS process. ...
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... C-bus master contains a start bit (SDA transition from HIGH to LOW Figures 3 (V2172) REGISTER nDATA ADDRESS (V2172) SLAVE ADDRESS 7 XR20V2172 2 2 C-bus specifications. The C-bus master contains a stop bit - 5 below. For complete details, see P STOP condition A P nDATA A LAST DATA ...
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... UART Channel Select ’00’ = UART Channel A ’01’ = UART Channel B 0 Reserved After the last read or write transaction, the I 2 C-bus. To distinguish itself from the other devices on the XR20V2172 ABLE DDRESS DDRESS VCC 0x60 (0110 000X) ...
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... PERATION FOR RANSMITTER FCR FCR B (FIFO D ) ISABLED HIGH = FIFO above trigger level LOW = FIFO below trigger level or FIFO empty HIGH = FIFO above trigger level LOW = FIFO below trigger level or transmitter empty 9 XR20V2172 Table 3 below. Table (FIFO NABLED ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER T ABLE FCR (FIFO D ISABLED IRQ# Pin HIGH = no data LOW = 1 byte 2.6 Crystal Oscillator or External Clock Input The V2172 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device ...
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... DLM = TRUNC(Required Divisor) >> 8 DLL = TRUNC(Required Divisor) & 0xFF DLL, DLM and DLD Registers MCR Bit-7=0 Prescaler (default) Divide by 1 Fractional Baud Rate Generator Logic Prescaler Divide by 4 MCR Bit-7=1 11 XR20V2172 Table 16X Sampling Rate Clock to Transmitter and Receiver ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156.25 10000 150 19200 78.125 25000 60 28800 52.0833 38400 39 ...
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... Transmit Shift Register (TSR FIFO AND LOW ONTROL ODE Transmit THR Interrupt (ISR bit-1) falls FIFO below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1 Transm it Data Shift Register (TSR) 13 XR20V2172 TXNOFIFO1 TXFIFO 1 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.9 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate ...
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... RHR Interrupt (ISR bit-2) programmed for Trigger=16 desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 Data fills to RTS# de-asserts when data fills to the Halt Level Halt Level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1. Receive Data Figure 12): 12): 15 XR20V2172 M ODE Receive Data Characters RXFIFO1 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re- asserted (LOW), indicating more data may be sent. F 12. A RTS CTS F IGURE UTO AND LOW Local UART ...
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... DLM and DLL registers is a non-zero value ■ sleep mode is enabled (IER bit ■ modem inputs are not toggling (MSR bits 0 ■ RXD input pin is idling LOW ■ (See Table 15), the V2172 compares one or two sequential receive data (See Table 17 XR20V2172 15) and suspend/resume ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER The V2172 UART portion stops its crystal oscillator to conserve power in this mode. The user can check the XTAL2 pin for no clock output as an indication that the device has entered the partial sleep mode. ...
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... Figure 13 below RANSMIT ATA NCODING AND Character Data Bits 3/16 or 1/4 Bit Time Bit Time Bit Time 1/16 Clock Delay Data Bits Character 19 XR20V2172 Figure 13 ECEIVE ATA ECODING 1 1/2 Bit Time IrEncoder IRdecoder-1 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.17 Internal Loopback The V2172 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 14 shows how the modem port signals are re-configured ...
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... Read-only Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read/Write Read/Write - Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 21 XR20V2172 C RITE OMMENTS LCR[ LCR[ LCR ≠ 0xBF LCR[ LCR ≠ 0xBF, EFR[ LCR[ LCR ≠ 0xBF Table 12 See Table 13 See Table 12 See Table 13 See ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER . T 8: INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDR AME RITE 0x00 RHR RD Bit-7 0x00 THR WR Bit-7 0x01 IER RD/WR 0/ CTS Int. RTS Int. Enable Enable 0x02 ISR RD FIFOs FIFOs ...
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... ISR [5:4], Flow FCR[5:4], Cntl MCR[7:5], Bit-3 DLD Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 23 XR20V2172 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR20V2172 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... RXRDY Time-out interrupt is cleared by reading RHR. • TXRDY interrupt is cleared by a read to the ISR register or writing to THR. • MSR interrupt is cleared by a read to the MSR register. • GPIO interrupt is cleared by reading the IOState register. • Xoff interrupt is cleared when Xon character(s) is received. 25 XR20V2172 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER • Special character interrupt is cleared by a read to ISR. • RTS# and CTS# flow control interrupts are cleared by a read to the MSR register ABLE P ISR R RIORITY EGISTER EVEL ...
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... This bit will return to a logic 0 after resetting the FIFO. FCR[3]: DMA Mode Select This is a legacy register bit that does not have any functionality in the XR20V2172. FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1) (logic 0 = default, TX trigger level = 1) These 2 bits set the trigger level for the transmit FIFO ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register ...
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... Logic 0 = Force RTS# HIGH (default). • Logic 1 = Force RTS# LOW. T 11: P ABLE ARITY SELECTION -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark, “1” Forced parity to space, “0” 29 XR20V2172 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER MCR[2]: OP1# / TCR and TLR Enable OP1# is not available as an output pin on the V2172. But it is available for use during Internal Loopback Mode (MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface signal ...
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... This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty. LSR[7]: Receive FIFO Data Error Flag • Logic FIFO error (default). 31 XR20V2172 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER • Logic global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO ...
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... This register is used to program the direction of the GPIO pins. Bit-7 to bit-0 controls GPIO7 to GPIO0. • Logic 0 = set GPIO pin as input • Logic 1 = set GPIO pin as output Table 13. This 8-bit register is used Table 14). For any non-zero value, TCR[7:4] will be 33 XR20V2172 10. ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.16 GPIO State Register (IOState) = Read/Write This register reports the state of all GPIO pins during a read and writes to any GPIO that is an output. • Logic 0 = set output pin LOW • Logic 1 = set output pin HIGH 4 ...
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... See DLD[ DLD[7:6]: Reserved “Section 2.16, Infrared Mode (UART Channel B SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH T 14 ABLE AMPLING ATE ELECT DLD[ XR20V2172 Table 14 below AMPLING ATE 16X 8X 4X ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.21 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting ...
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... Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH. Data transmission resumes when CTS# returns LOW. 4.21.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, see Table 8. 37 XR20V2172 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REGISTERS DLM, DLL DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR TCR TLR TXLVL RXLVL IODir IOState IOIntEna IOCont EFCR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX RTS# ...
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... REV. 1.0.0 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (64-QFN) 6 Volts GND-0.3V to VCC o o - -65 to +150 C ) MARGIN OF ERROR: ± 15% o theta- C/W, theta- XR20V2172 o C/W ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER E C LECTRICAL HARACTERISTICS U : TA= -40 NLESS OTHERWISE NOTED P SYMBOL ARAMETER DC C HARACTERISTICS I Supply Current, Normal Mode Supply Current, Sleep Mode/Power- SLP PWS Save Mode O I (X1) SCILLATOR NPUT V Clock Input Low Level ...
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... Unless otherwise noted: TA=-40 to +85 S YMBOL XTAL1 UART Crystal Oscillator ECLK UART External Clock T External Clock Time Period ECLK F 15 IGURE LOCK IMING VIHCK External Clock VILCK o C, Vcc=3.3 - 5.5V P ARAMETER T ECLK T ECH 41 XR20V2172 L IMITS U NIT MHz 64 MHz ECL ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS o Unless otherwise noted: TA=- YMBOL f Operating frequency SCL T Bus free time between STOP and START BUF T START condition hold time HD;STA T START condition setup time SU ...
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... SDA T HD;STA F 18 IGURE RITE O UTPUT SLAVE SDA ADDRESS GPIOn T D15 Bit 7 Bit 0 Bit 6 MSB LSB (A6) (A7) (R/W) T HIGH 1/F SCL SU;DAT HD;DAT W A IOSTATE REG XR20V2172 STOP Acknowledge condition (A) ( VD;DAT VD;ACK SU;STO DATA ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 19 IGURE ODEM NPUT IN NTERRUPT SLAVE SDA W ADDRESS IRQ MODEM pin F 20. GPIO P I IGURE IN NTERRUPT SLAVE SDA W A ADDRESS IRQ# GPIOn SLAVE A MSR REGISTER A S ADDRESS ...
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... ECEIVE NTERRUPT LEAR SLAVE SDA W A ADDRESS IRQ IGURE RANSMIT NTERRUPT SLAVE SDA W ADDRESS IRQ SLAVE RHR A S ADDRESS LEAR A THR REGISTER A DATA 45 XR20V2172 Next start Stop bit bit DATA DATA ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS o Unless otherwise noted: TA=- YMBOL T CS# HIGH to SO three-state time TR T CS# to SCL setup time CSS T CS# to SCL hold time CSH T SCL fall to SO valid time ...
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... DTR O IGURE RITE TO CS# SCLK SI R GPIOx F 26. SPI W MCR DTR O IGURE RITE TO CS# SCLK SI R DTR# (GPIO5) S UTPUT WITCH A0 CH1 CH0 UTPUT WITCH A0 CH1 CH0 XR20V2172 D10 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 27. SPI W THR C IGURE RITE TO LEAR CS# SCLK SI R GPIOx IRQ# F 28. R MSR C M IGURE EAD TO LEAR CS# SCLK SI R IRQ# TX INT A0 CH1 CH0 INT ODEM A0 CH1 CH0 ...
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... TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. 1.0.0 F 29. R IOS C IGURE EAD TATE TO LEAR CS# SCLK SI R IRQ# F 30. R RHR C RX INT IGURE EAD TO LEAR CS# SCLK SI R IRQ# GPIO INT A0 CH1 CH0 D13 A0 CH1 CH0 D14 49 XR20V2172 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER PACKAGE DIMENSIONS (64 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0 ...
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... EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet July 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. D ESCRIPTION NOTICE 51 XR20V2172 ...
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... IGURE ASTER RITES O LAVE IGURE ASTER EADS ROM LAVE 2.2 I2C-BUS ADDRESSING ...................................................................................................................................... XR20V2172 I2C A M ABLE DDRESS T 2: I2C S -A ............................................................................................................................................................ 8 ABLE UB DDRESS 2.2.1 SPI BUS INTERFACE ..................................................................................................................................................... SPI .................................................................................................................................................. 9 ABLE IRST YTE ORMAT 2.3 DEVICE RESET ................................................................................................................................................... 9 2 ...
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... XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 23 4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 24 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 24 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ...