xr20v2172 Exar Corporation, xr20v2172 Datasheet - Page 26

• Manufacturer Part Number: xr20v2172
• Description: Two Channel I2c/spi Uart With 64-byte Fifo And Rs232 Transceiver
• Manufacturer: Exar Corporation

XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
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ISR[0]: Interrupt Status
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•
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is set when EFR[4] = 1 and IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of
the Xoff character(s). If this is an Xoff interrupt, it is cleared when XON is received. If it is a special character
interrupt, it is cleared by reading ISR.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR[4] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
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•
4.5
P
Special character interrupt is cleared by a read to ISR.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
RIORITY
L
EVEL
1
2
3
4
5
6
7
8
-
FIFO Control Register (FCR) - Write-Only
B
IT
0
0
0
0
0
1
0
1
0
-5
B
IT
0
0
0
0
0
1
1
0
0
-4
ISR R
B
EGISTER
IT
T
0
1
0
0
0
0
0
0
0
ABLE
-3
B
9: I
S
IT
TATUS
1
1
1
0
0
0
0
0
0
-2
NTERRUPT
B
B
ITS
IT
1
0
0
1
0
0
0
0
0
-1
S
OURCE AND
26
B
IT
0
0
0
0
0
0
0
0
1
-0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
GPIO (General Purpose Inputs)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default)
P
RIORITY
L
EVEL
S
OURCE OF INTERRUPT
REV. 1.0.0
Table
9).