xr20v2172 Exar Corporation, xr20v2172 Datasheet - Page 9

• Manufacturer Part Number: xr20v2172
• Description: Two Channel I2c/spi Uart With 64-byte Fifo And Rs232 Transceiver
• Manufacturer: Exar Corporation

REV. 1.0.0
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 5 Mbps. To access the device in the SPI
mode, the CS# signal for the V2172 is asserted by the SPI master, then the SPI master starts toggling the SCL
signal with the appropriate transaction information. The first byte sent by the SPI master includes whether it is
a read or write transaction and the UART register being accessed. See
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
The RESET# input resets the internal registers and the serial interface outputs in the UART to its default state
(see
in the device.
The V2172 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to the industry standard ST16C550. These registers function as data
holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR),
receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR),
programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible Scratchpad Register
(SPR).
Beyond the general 16C550 features and capabilities, the V2172 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, TCR, TLR, TXLVL, RXLVL, IODir, IOState, IOIntEna, IOControl, EFCR and DLD) that
provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, TX and RX FIFO level
counters, and programmable FIFO trigger level control. All the register functions are discussed in full detail
later in
The IRQ# interrupt output changes according to the operating mode and enhanced features setup.
and 5
2.3
2.4
2.5
2.2.1
IRQ# Pin
IRQ# Pin
Table
summarize the operating behavior for the transmitter and receiver.
“Section 3.0, UART Internal Registers” on page
Device Reset
Internal Registers
IRQ# Output
SPI Bus Interface
16). An active low pulse of longer than 40 ns duration will be required to activate the reset function
Auto RS485
Mode
YES
NO
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
B
6:3
2:1
7
0
IT
T
HIGH = a byte in THR
LOW = THR empty
HIGH = a byte in THR
LOW = transmitter empty
ABLE
Read/Write#
Logic 1 = Read
Logic 0 = Write
UART Internal Register Address A3:A0
UART Channel Select
’00’ = UART Channel A
’01’ = UART Channel B
Reserved
(FIFO D
FCR B
4: IRQ# P
T
ABLE
IT
ISABLED
3: SPI F
-0 = 0
IN
O
)
PERATION FOR
IRST
9
F
UNCTION
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or FIFO empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or transmitter empty
B
21.
YTE
F
ORMAT
T
RANSMITTER
FCR B
Table 3
IT
-0 = 1 (FIFO E
below.
NABLED
XR20V2172
)
Table 4