71m6545h-igtr/f Maxim Integrated Products, Inc., 71m6545h-igtr/f Datasheet - Page 31

• Manufacturer Part Number: 71m6545h-igtr/f
• Description: Metrology Processors
• Manufacturer: Maxim Integrated Products, Inc.

organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas:
PDS_6545_009
Typical measurement and metering functions based on the results provided by the internal 32-bit compute
engine (CE) are available for the MPU as part of the Teridian demonstration code, which is provided to
help reduce the product design cycle.
2.4.3 Memory Organization and Addressing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory
Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,
Configuration or I/O RAM), and internal data memory (Internal RAM).
Program Memory
The 80515 can address up to 64 KB of program memory space (0x0000 to 0xFFFF). Program memory is
read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from program memory location 0x0000. The lower part of
the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte
intervals, starting from 0x0003.
MPU External Data Memory (XRAM)
Both internal and external memory is physically located on the 71M6545/H device. The external memory
referred to in this documentation is only external to the 80515 MPU core.
5 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, leaving 4 KB for the MPU. Different versions of the CE code use varying amounts. Consult the
documentation for the specific code version being used for the exact limit.
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX
A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes for the MOVX A,@Ri instruction).
Internal and External Memory Map
Table 9
v1.0
0000-FFFF
Address
(hex)
If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is
disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 (I/O RAM
0x2100[7:3]), because the 71M6545/H ADC writes to these locations. Writing MUX_DIV[3:0] = 0
disables the ADC output, preventing the CE from writing the first 0x40 bytes of RAM.
In addition, MUXn_SEL[3:0] values must be written only after writing MUX_DIV[3:0].
shows the address, type, use and size of the various memory components.
Flash Memory
Technology
Memory
© 2008–2011 Teridian Semiconductor Corporation
MPU_DIV [2:0]
Non-volatile Program memory
010
011
100
101
110
111
Memory
Type
Table 9: Memory Map
CKMPU Frequency
Name
1.2288 MHz
614.4 kHz
307.2 kHz
Table 9
MPU Program and
non-volatile data
Typical Usage
CE program
shows the memory map.
Data Sheet 71M6545/H
Memory Size
3 KB max.
(bytes)
64 KB
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