pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 19

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Figure 19 Bit Delay from RXD0/CDR to TXD1/TXD0
Test Functions
A test loop is provided in each of the four HDLC controllers
of the PT7A6527. When the test loop is activated, the input
and the output of the HDLC channel are connected together.
The test loop control is independent for each HDLC channel
(bit TLP).
The test loop is either transparent (forward data is outputted
on the line) or non-transparent (forward data is not outputted
on the line), depending on the selected mode. In the quad
connection common control mode and in the single
connection IOM mode the loops are transparent. In the other
cases they are non-transparent. During a non-transparent loop,
the data output is high impedance inside the assigned time
channel.
Preprocessed Channels
The PT7A6527 supports the Command/Indicate (C/I) channel
at the IOM-2 interface. The C/I handler takes care of the C/I
channels.
C/l Channel Handler
PT0080(02/09)
a) Bit delay for coinciding channel/time slot position on RXD0/TXD0 and on CDR/TXD1
b) Bit delay for non-identical channel/time slot position on RXD0/TXD0 and on CDR/TXD1 (possible only when
RXD0/TXD0 is an IOM interface)
RXD0
TXD0
CDR
TXD1
RXD0
TXD0
CDR
TXD1
19
To activate the C/I handler, CCR: CDEN is set to “1”. The C/I
handler can be used in the following switching modes:
-
-
and in the following bus access modes:
- unconditional transmission
- master
- multi master (only 1 C/I transmitter is allowed per
In the upstream direction the signaling handler MONITORS
the received C/I channels. Upon a change
-
-
Only single last look is carried out. The C/I channel is
sampled in each frame. The change detection only operates on
the 4-bit C/I channel.
The ISTAn: CD interrupt is cleared when ISTAn is read. In
the downstream direction the value written to CIX3 ... CIX0
will be sent in the C/I channels in each frame.
subscriber).
single connection IOM mode
single connection time-slot mode
an interrupt is generated (ISTAn: CD)
the actual value is stored in registers CIR3 ... CIR0.
HDLC controller
Data Sheet
PT7A6527
Ver:4