pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 29

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Command Register (CMDR)
-- Address: Base + 21/28H (Base + 11H) Write, Value after reset: 00H
Bit
Mode Register (MODE)
-- Address: Base + 22/2BH (Base + 12H) Read/Write, Value after reset: 00H
Bit
Note: The bit rates given above assume a channel repetition rate of 8 kHz.
Commond/Indicate Channel Receive Channel 0 - 3 (CIR0 - 3)
-- Address: Base + 23/2AH (Base + 13H) Read, Value after reset: 0FH
PT0080(02/09)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
CCS1
Name
RRES
XRES
CMS1
CMS0
Name
CCS1
CCS0
RMC
RMD
XME
XHF
RAC
CAC
0
0
1
1
FHF
TLP
ITF
X
Name
CI3
CI2
CI1
CI0
n
n
n
n
Receive Message Complete: When 1, confirms by microprocessor to chip, that the actual frame or data block has
been fetched following an RPF or RME interrupt; thus, the occupied space in the RFIFO can be released.
Receiver Reset: When 1, all data in the RFIFO and the HDLC receiver are deleted.
Receive Message Delete. Reaction to RPF or RME interrupt. The entire frame is to be ignored by the receiver.
The part of the frame already stored is discarded.
Transmit HDLC Frame. Transmission of an HDLC frame (or of a block thereof) is initiated
Force HDLC Frame. Used in the master collision mode (CMS1,0 = 11). When this bit is set and a Transmit
HDLC Frame (XHF) command is issued, the controller aborts the frame from CDR (if any) by sending seven 1's
on TXD0 and then starts transmission. TXD2 is set ""low"" to indicate that no data will be accepted on CDR
input data line.
Transmit Message End: When 1, indicates that the data block last written to the transmit FIFO completes the
actual frame. The chip can terminate the transmission operation properly by appending the CRC and the closing
flag sequence to the data.
Transmitter Reset. The HDLC transmitter is reset, XFIFO is cleared of any data and the HDLC frame currently
transmitted (if any) is aborted.
Test Loop: Input and output of HDLC channel are connected together when TLP = 1. The test loop is either
transparent (if MDS1,0 = 01, 10) or not (if MDS1,0 = 00, 11).
CMS1,0 Collision Mode Select:
CMS1 CMS0 = 0 0, Unconditional transmission
CMS1 CMS0 = 0 1, Slave mode
CMS1 CMS0 = 1 0, Multi-master mode
CMS1 CMS0 = 1 1, Master mode
Interframe Time Fill: Idle (ITF = 0) or flags (ITF = 1) are used as interframe time fill.
Receiver Active: Receiver is activated (1) or deactivated (0).
Channel Active: A channel is completely disabled (receiver and transmitter are inactive, transmit line is high
impedance, no TSC is output) as long as CAC is "0".
Channel Capacity Select: These bits select the number of bits in the time slot where data are received and
transmitted. They have a significance only when MDS1,0 = 00 or 11 (Single connection TS mode and Quad
connection TS mode). Refer to next table.
CCS0
Not used
Received C/I code, will be updated in each frames. CI3 is received first.
0
1
0
1
Time-Slot Width
2 bits
1 bits
8 bits
7 bits
29
Description
Description
Description
Channel Data Rate (kbit/s)
16
64
56
8
HDLC controller
Data Sheet
PT7A6527
Ver:4