pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 28

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
XFIFO - If more than 32 bytes are written to the XFIFO
(without a transmit command), an XDOV interrupt is
generated. The byte that was entered first (first byte to be sent)
will be continuously overwritten by the extra write operations.
Status Byte:
Bit
A status byte equal to A0H indicates a correctly received frame.
Interrupt Status Register (ISTA)
-- Address: Base + 20/29H (Base + 10H) Read, Value after reset: 00H
Bit
Note: It is not possible to transmit frames when an XDU interrupt remains unacknowledged.
Mask for Interrupt Status Register (ISM)
--Address: Base + 20/29H (Base + 10H) Write, Value after reset: 00H
Each interrupt source in ISTA register can be selectively masked by setting to 1 the corresponding bit in ISM. Masked interrupts
are not indicated when ISTA is read. Instead, they remain internally stored and pending. An interrupt is generated after the mask is
reset to zero.
Status Register (STAR)
-- Address: Base + 21 /28H (Base + 11H) Read, Value after reset: 52H
Bit
PT0080(02/09)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Name
Name
XDOV
RME
XDU
RDO
RAB
Name
RBC
CRC
RFO
XPR
XFW
RPF
RNA
BSY
VN3
VN2
VN1
VN0
CD
0
0
0
0
n
n
Receive byte count: The length of the received frame (excluding flags and Frame Check Sequence FCS) is N x 8
bits if RBC = 1 (N = 1,2,3...). The length is not a multiple of 8 bits if RBC = 0.
Receive Data Overflow: If RDO = 1, part of the frame has been lost because the receive FIFO was full.
CRC Check: The received FCS bytes were correct if CRC = 1.
Receive Abort: RAB = 1 implies that the received frame was aborted.
-
-
-
-
Receive Message End: One complete frame of length less than 32 bytes, or the last part of a frame at least 32
bytes long is stored in the receive FIFO, including the status byte. The number of bytes stored is given by RFBC
bits 0-4.
Receive Pool Full: 32 bytes of a frame have arrived in the receive FIFO. The frame is not yet completely
received.
Receive Frame Overflow: At least one complete frame was lost because no storage space was available in the
RFIFO.
Transmit Pool Read: When it is 1, indicates that a data block of up to 32 bytes can be written to the transmit
FIFO.
Transmit Data Underrun: Transmitted frame was terminated with an abort sequence either 1) no data was
available for transmission in XFIFO and no XME command was issued, or
least one block of data has been completely transmitted, thus an automatic retransmission cannot be attempted.
Change detection interrupt: A new value has been entered into the CIR register.
Transmit Data Overflow: When 1, indicates that more than 32 bytes have been written to the XFIFO
Transmit FIFO Write Enable: When 1, indicates that data can be written to the XFIFO.
Busy state on the receive line. ""0"" in this bit position indicates an ""idle"" state on the input data line (15 or
more consecutive ones).
Receive line Not Active. Indicates whether flags/frames are being received on the line (0) or not (1). RNA takes
on the value ""1"" after seven consecutive ones are received on the line.
Version Number of chip: VN3 VN2 VN1 VN0 = 0010
Bit 7
RME
RPF
RFO
XPR
28
Description
Description
Description
XDU
When the closing flag of a receive frame is detected, a status
byte is appended to the data in the RFIFO.
n
cd
2) a collision has occurred after at
Bit 0
n
HDLC controller
Data Sheet
PT7A6527
Ver:4