wm8988 Wolfson Microelectronics plc, wm8988 Datasheet - Page 46

• Manufacturer Part Number: wm8988
• Description: Stereo Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

WM8988
Highlighting indicates bits or registers which differ from WM8750L / WM8750BL device family.
w
REGISTER
R10 (0Ah)
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R15 (0Fh)
R26 (1Ah)
R27 (1Bh)
R31 (1Fh)
R42 (2Ah)
R16 (10h)
R17 (11h)
R18 (12h)
R19 (13h)
R20 (14h)
R21 (15h)
R22 (16h)
R23 (17h)
R24 (18h)
R25 (19h)
R32 (20h)
R33 (21h)
R34 (22h)
R35 (23h)
R36 (24h)
R37 (25h)
R38 (26h)
R39 (27h)
R40 (28h)
R41 (29h)
R67 (43h)
REGISTER MAP
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
R9 (09h)
(Bit 15 – 9)
ADDRESS
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
1000011
Additional Control (3)
Low Power Playback
Additional control(1)
Additional control(2) LCOMEN
ADC & DAC Control ADCDIV2 DACDIV2
Right Input volume
Right DAC volume
Right ADC volume
ADCR signal path
ADCL signal path
Left Input volume
Left DAC volume
Left ADC volume
Right out Mix (1)
Right out Mix (2)
ADC input mode
ROUT1 volume
Left out Mix (1)
ROUT2 volume
LOUT1 volume
Audio Interface
Left out Mix (2)
LOUT2 volume
Treble control
Pwr Mgmt (1)
Pwr Mgmt (2)
Sample rate
Bass control
Noise Gate
3D control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
remarks
Reset
ALC1
ALC2
ALC3
RO1VU
TSDEN
RD2RO
RO2VU
LO1VU
RD2LO
LD2RO
LO2VU
LD2LO
RDVU
RAVU
Bit[8]
LDVU
LAVU
DACL
RIVU
LIVU
VMIDSEL[1:0]
DS
ALCSEL[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BCM[1:0]
00
RINMUTE
LINMUTE
BCLKINV
MODE3D
HPCOMEN
RO1ZC
RO2ZC
LO1ZC
ALCZC
LO2ZC
RI2RO
DACR
RI2LO
LI2RO
LI2LO
Bit[7]
MONOMIX[1:0]
BB
RINSEL[1:0]
LINSEL[1:0]
0
0
0
0
0
0
0
0
VSEL[1:0]
writing to this register resets all registers to their default state
CLKDIV2
LOUT1
3DUC
Bit[6]
VREF
RIZC
VROI
LIZC
MS
ADCPOL[1:0]
BC
TC
0
0
0
0
0
1
1
1
0
DCY[3:0]
RI2ROVOL[2:0]
RI2LOVOL[2:0]
LI2ROVOL[2:0]
LI2LOVOL[2:0]
MAXGAIN[2:0]
NGTH[4:0]
LRSWAP
HPFLREN
ROUT1
RMICBOOST[1:0]
RDCM
LMICBOOST[1:0]
DMONOMIX[1:0]
Bit[5]
3DLC
AINL
0
0
0
0
0
0
0
0
0
1
0
LOUT2
HPOR
LDCM
Bit[4]
AINR
LRP
LDACVOL[7:0]
RDACVOL[7:0]
LADCVOL[7:0]
RADCVOL[7:0]
0
0
0
0
0
0
0
1
1
0
1
0
LOUT1VOL[6:0]
ROUT1VOL[6:0]
LOUT2VOL[6:0]
ROUT2VOL[6:0]
DACMU
SR[4:0]
ROUT2
Bit[3]
ADCL
DACMIX
3DDEPTH[3:0]
TRI
DATSEL[1:0]
BIAS
0
0
0
0
0
0
0
0
0
0
0
0
0
1
WL[1:0]
RINVOL
LINVOL
LRCM
ADCR
Bit[2]
DEEMPH[1:0]
0
0
0
NGG[1:0]
0
0
0
0
0
0
0
0
0
0
0
BASS[3:0]
TRBL[3:0]
ALCL[3:0]
HLD[3:0]
ATK[3:0]
RMIXSEL[2:0]
LMIXSEL[2:0]
ADCOSR DACOSR
DACINV
Bit[1]
0
0
0
0
0
0
0
FORMAT[1:0]
0
0
0
0
0
0
0
0
ADCHPD
DIGENB
NGAT
Bit[0]
3DEN
USB
TOEN
0
0
0
0
0
0
0
PD, Rev 4.0, October 2008
0
0
0
0
0
1
0
010010111
010010111
001111001
001111001
000000000
000001000
000000000
000001010
000000000
000000000
011111111
011111111
000001111
000001111
000000000
001111011
000000000
000110010
000000000
011000011
011000011
011000000
000000000
000000000
000000000
000000000
000000000
000000000
000000000
001010000
001010000
001010000
001010000
001010000
001010000
001111001
001111001
001111001
000000000
not reset
default
Production Data
18,19,28,33
page ref
19,25,28
19
19
31
31
37
39
26
26
27
27
25
23
23
23
24
21
21
43
43
35
17
17
17
29
29
30
30
30
30
32
32
35
50
-
-
-
-
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