wm8941 Wolfson Microelectronics plc, wm8941 Datasheet - Page 13
wm8941
Manufacturer Part Number
wm8941
Description
Mono Codec With Speaker Driver And Video Buffer
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8941.pdf
(94 pages)
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Production Data
w
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Note 1:
PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
AUDIO INTERFACE TIMING – MASTER MODE
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD=1.8V, AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T
PARAMETER
System Clock Timing Information
MCLK cycle time
MCLK duty cycle
MCLK
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
SYMBOL
T
T
MCLKDS
MCLKY
t
MCLKL
t
MCLKY
MCLK=SYSCLK (=256fs)
t
MCLKH
MCLK input to PLL
CONDITIONS
A
= +25
Note 1
o
C
81.38
60:40
20
MIN
TYP
PD, Rev 4.0, August 2008
40:60
MAX
WM8941
UNIT
ns
ns
13
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