wm8750 Wolfson Microelectronics plc, wm8750 Datasheet - Page 39

• Manufacturer Part Number: wm8750
• Description: Stereo Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

Production Data
w
DIGITAL AUDIO INTERFACE
LINE OUTPUT
The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs.
Additionally, OUT3 and MONOOUT can be used as a stereo line-out by setting OUT3SW=11 (reg.
24) and ensuring the contents of registers 38 and 39 (mono-out mix) are the same as reg. 34 and 35
(left out mix). Recommended external components are shown below.
Figure 15 Recommended Circuit for Line Output
The DC blocking capacitors and the load resistance together determine the lower cut-off frequency,
f
f
Increasing the capacitance lowers f
diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage
when used improperly.
The digital audio interface is used for inputting DAC data into the WM8750L and outputting ADC data
from it. It uses five pins:
•
•
•
•
•
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8750L operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
•
•
•
•
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8750L can be configured as either a master or slave mode device. As a master device the
WM8750L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data
transfer on ADCDAT and DACDAT. In slave mode, the WM8750L responds with data to clocks it
receives over the digital audio interface. The mode can be selected by writing to the MS bit (see
Table 23). Master and slave modes are illustrated below.
Figure 16 Master Mode
c
c
. Assuming a 10 kOhm load and C1, C2 = 1µF:
= 1 / 2π (R
WM8750L
ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
DACDAT: DAC data input
DACLRC: DAC data alignment clock
BCLK: Bit clock, for synchronisation
Left justified
Right justified
I
DSP mode
2
Note: The ADC and DAC can run at different sample rates
S
WM8750
CODEC
L
+R
or OUT3 (OUT3SW=11)
1
ADCLRC
DACLRC
ADCDAT
DACDAT
) C
BCLK
1
or MONOOUT
= 1 / (2π x 10.1kΩ x 1µF) = 16 Hz
ROUT1/2
LOUT1/2
ENCODER/
DECODER
1uF
1uF
c
DSP
C1
C2
, improving the bass response. Smaller values of C1 and C2 will
100 Ohm
100 Ohm
R1
R2
AGND
AGND
Figure 17 Slave Mode
LINE-OUT
LINE-OUT
SOCKET
SOCKET
(RIGHT)
(LEFT)
Note: The ADC and DAC can run at different sample rates
WM8750
CODEC
ADCLRC
DACLRC
ADCDAT
DACDAT
BCLK
PD Rev 4.3 October 2006
WM8750L
ENCODER/
DECODER
DSP
39