wm8782a Wolfson Microelectronics plc, wm8782a Datasheet - Page 13

• Manufacturer Part Number: wm8782a
• Description: 24-bit, 192khz Stereo Adc
• Manufacturer: Wolfson Microelectronics plc

Production Data
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MASTER CLOCK AND AUDIO SAMPLE RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock (MCLK). The external master system clock can be applied directly through the MCLK
input pin. In a system where there are a number of possible sources for the reference clock it is
recommended that the clock source with the lowest jitter be used to optimise the performance of the
ADC.
The master clock is used to operate the digital filters and the noise shaping circuits. The WM8782A
supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio
sampling frequency (LRCLK). In Slave Mode, the WM8782A automatically detects the audio sample
rate.
Table 5 shows the common MCLK frequencies for different sample rates.
Table 5 Master Clock Frequency Selection
In Slave mode, the WM8782A has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available
(768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8782A is tolerant of
phase variations or jitter on these clocks.
FSAMPEN
The FSAMPEN pin controls the over sampling rate of the ADC. The WM8782A can operate at
sample rates from 8kHz to 192kHz. The WM8782A uses a sigma-delta modulator that operates at an
optimal frequency of 6.144MHz.
By default the WM8782A generates the ADC frequency at 128xOSR. At fs=48kHz, the ADC
frequency is 128xOSR = 128x48kHz = 6.144MHz.
If fs=96KHz, the FSAMPEN pin must be set to 1. In this case, the ADC frequency is 64xOSR =
64x96kHz = 6.144MHz.
If fs=192KHz, the FSAMPEN pin must be set to z. In this case, the ADC frequency is 32xOSR =
32x192kHz = 6.144MHz.
Table 6 Sampling Rate Enable Selection
FSAMPEN
SAMPLING RATE
44.1kHz
192kHz
PIN
(LRCLK)
16kHz
32kHz
48kHz
96kHz
8kHz
Fast sampling rate enable
0 = 48ken (128x OSR)
1= 96ken (64x OSR)
z= 192ken (32x OSR)
Master Clock Frequency (MHz)
5.6448
12.288
24.576
1.024
2.048
4.096
6.144
128fs
DESCRIPTION
18.432
36.864
1.536
3.072
6.144
8.467
9.216
192fs
11.2896
12.288
24.576
2.048
4.096
8.192
256fs
-
16.9340
12.288
18.432
36.864
3.072
6.144
384fs
-
22.5792
16.384
24.576
4.096
8.192
512fs
-
-
PD, April 2010, Rev 4.8
33.8688
12.288
24.576
36.864
6.144
768fs
WM8782A
-
-
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