isppac-clk5520v-01tn100 Lattice Semiconductor Corp., isppac-clk5520v-01tn100 Datasheet - Page 16

• Manufacturer Part Number: isppac-clk5520v-01tn100
• Description: In-system Programmable Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
above reasons, it is recommended that when using phase-detect mode, the user wait a small amount of time
(~25µs) between the time the LOCK signal is first asserted and the time at which the output clock signals are
assumed to be completely stable.
When the lock condition is lost the LOCK signal will be de-asserted immediately in both phase-lock and frequency-
lock detection modes. In frequency-lock mode, however, if the input reference signal is stopped, the LOCK output
may continue to be asserted. In phase-lock mode, a loss of the input reference signal will always result in de-asser-
tion of the LOCK output.
Loop Filter
A simplified schematic for the ispClock5500 loop filter is shown in Figure 11. The filter’s capacitors are fixed, and
the response is controlled by setting the value of the phase-detector’s output current source’s and the value of the
variable resistor. The phase detector output current has 14 possible settings, ranging from 3µA to 55µA, while the
resistor may be set to any one of six values ranging from 2.3K to 9.3K. This provides a total of 84 unique I-R com-
binations which may be selected.
Figure 11. ispClock5500 Loop Filter (Simplified)
Because the selection of an optimal PLL loop filter can be a daunting task, PAC-Designer offers a set of default fil-
ter settings which will provide acceptable performance for most applications. The primary criterion for selecting one
of these settings is the total division factor used in the feedback path. This factor is the ratio between the VCO out-
put frequency and the feedback V-divider output frequency which is the product of the N-divider and V
divider (N x V
Table 2. PAC-Designer Recommended Loop Filter Settings
The choice of loop filter parameters can have significant effects on settling time, output jitter, and whether the PLL
will be fundamentally stable and be able to lock to an incoming signal. The values recommended in Table 2 were
feedback
). Table 2 lists these default settings and conditions under which they should be used.
M-divider
N-divider
From
From
N x V
12 to 14
18 to 20
24 to 26
32 to 64
2 to 8
Phase Detector
10
16
22
28
30
FBK
I
I
I (µA)
16
11
13
15
17
19
21
22
5
7
9
C
1
R (kΩ)
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
ispClock5500 Family Data Sheet
R
C
2
To VCO
feedback
-