lfx125ec-04fh516c Lattice Semiconductor Corp., lfx125ec-04fh516c Datasheet - Page 9

• Manufacturer Part Number: lfx125ec-04fh516c
• Description: Ispxpga Family
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Set/Reset signal controls all the registers for each PFU. This common Set/Reset signal is composed of the logical
OR term of the Global Set/Reset signal (GSR) and the selected signal from routing. The polarity of this signal is not
controllable inside the PFU. The polarity of the Global Set/Reset signal (GSR) is programmable. Figure 9 shows
the Clock Enable and Output Enable selection for each PFU.
Figure 7. Clock Selection per PFU
Figure 8. Set/Reset Selection per PFU
Figure 9. Clock Enable and Output Enable Selection per PFU
Programmable Input/Output Cell
The Programmable Input/Output Cell (PIC) is an essential part of the symmetrical architecture of the ispXPGA
Family. The PICs interface the PFUs and EBRs to the sysIO and sysHSI blocks of the device.
Each PIC contains two Programmable Input/Outputs (PIOs) with a total of 21 inputs and 10 outputs. There are 18
inputs from routing, two inputs from the sysIO buffers, and the Global Set/Reset signal. Four outputs of the PIC
connect to routing and two outputs are available as Output Enables for the tri-statable Long Lines. The remaining
four outputs feed the sysIO buffers directly (one output enable and one output to each). Each PIC associated with
a sysHSI block has four additional inputs and six additional outputs to support the sysHSI blocks. The four addi-
tional inputs come from the sysHSI block associated with the PIC. The four of the six additional outputs come from
the PIC outputs and feed the sysHSI block, while the remaining two outputs feed routing. Figure 10 shows the
block diagram of the PIC with the sysHSI block inputs and outputs.
From routing
From routing
GSR
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
8
From routing
From routing
4
8
8
9
CEB0
CEB1
OE
ispXPGA Family Data Sheet
PFUCLK0
PFUCLK1
Set/Reset