lfe3-150ea-8fn672itw Lattice Semiconductor Corp., lfe3-150ea-8fn672itw Datasheet - Page 125
lfe3-150ea-8fn672itw
Manufacturer Part Number
lfe3-150ea-8fn672itw
Description
Latticeecp3 Family Data Sheet
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.LFE3-150EA-8FN672ITW.pdf
(136 pages)
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Company:
Part Number:
LFE3-150EA-8FN672ITW
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Logic Signal Connections
Package pinout information can be found under “Data Sheets” on the LatticeECP3 product pages on the Lattice
website at
pinout information from within ispLEVER Design Planner, select View > Package View. Then select Select File >
Export and choose a type of output file. To create a pin information file from within Diamond select Tools >
Spreadsheet View or Tools >Package View; then, select File > Export and choose a type of output file. See Dia-
mond or ispLEVER Help for more information.
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package
specific thermal values.
For Further Information
For further information regarding Thermal Management, refer to the following:
•
• TN1181,
• Power Calculator tool included with the Diamond and ispLEVER design tools, or as a standalone download from
Thermal Management
www.latticesemi.com/software
www.latticesemi.com/products/fpga/ecp3
Power Consumption and Management for LatticeECP3 Devices
document
and in the Diamond or ispLEVER software tools. To create
4-10
LatticeECP3 Family Data Sheet
Pinout Information
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