pacvga203 California Micro Devices Corporation, pacvga203 Datasheet
pacvga203
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pacvga203 Summary of contents
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... California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 12/07/04 VGA Port Companion Circuit Product Description The PACVGA203 incorporates seven channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-2 Level- 4 ESD Protection (8kV contact discharge) ...
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... V_BIAS. In applications where powered down, diode D1 blocks any DC current paths from the DDC_OUT pins back to the powered down V CC The PACVGA203 device is housed in a 24-pin QSOP package and is available with optional lead-free finish- ing. PACKAGE / PINOUT DIAGRAM Top View 1 ...
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... Vertical Sync signal). Sync Signal Filter 2. Connects to the video connector side of one of the sync lines (for example the Horizontal Sync signal). Tel: 408.263.3214 G PACVGA203 pin for the SYNC_1, SYNC_2, SD1 CC pin for the VIDEO_1, VIDEO_2 and CC pin for the DDC_IN1 and DDC_IN2 ...
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... PWR-UP pin SYNC outputs CC unloaded 5.0V; SYNC inputs at 3.0V; PWR-UP CC pin SYNC outputs unloaded 5.0V; PWR-UP input at GND; SYNC CC outputs unloaded Tel: 408.263.3214 G PACVGA203 RATING [GND - 0.5] to +6.0 100 -40 to +85 -65 to +150 (GND - 0. 0.5) CC -6.0, +6.0 (GND - 0. 0.5) CC (GND - 0. 0.5) CC (GND - 0 ...
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... 50pF; V =5.0V,Input t and 50pF; V =5.0V; Input t and 50pF; V =5.0V; Input t and (measured 10 5V; Notes 3 & Tel: 408.263.3214 G G PACVGA203 (CONT’D) MIN TYP MAX 2.0 0.8 4.94 0. 0.5 1.0 2.0 0.5 1.5 3 0.15 3.0 4.0 5.0 3.0 4.5 5.6 < 5ns 8 ...
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... SYNC_IN signal frequency varies. A square wave CC Figure SYNC_IN 3.3V 0V Figure 1. Sync Buffer I 4 Test Circuit CC I vs. SYNC_IN Frequency CC4 Frequency, kHz 4 vs. SYNC_IN Frequency Performance Data CC Tel: 408.263.3214 G PACVGA203 + SYNC_OUT C1 100pF 50pF 0pF 80 100 Fax: 408.263.7846 www.calmicro.com G G ...
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... A resistor may be necessary between the V required while the PACVGA203 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into the V ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second ...
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... Mechanical Details QSOP Mechanical Specifications: PACVGA203 devices are packaged in 24-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-24 package, see the California Micro Devices QSOP Package Infor- mation document. PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins Millimeters ...