adum3100 Analog Devices, Inc., adum3100 Datasheet - Page 6

• Manufacturer Part Number: adum3100
• Description: Digital Isolator, Enhanced System-level Esd Reliability
• Manufacturer: Analog Devices, Inc.

ADuM3100
Parameter
1
2
3
4
5
6
7
8
9
10
t
rising edge of the V
distortion can be affected by slow input rise/fall times. See the System-Level ESD Considerations and Enhancements section and Figure 13 to Figure 17 for information
on the impact of given input rise/fall times on these parameters.
t
recommended operating conditions. t
temperature, supply voltages, and output load within the recommended operating conditions.
that can be sustained while maintaining V
over which the common-mode is slewed.
All voltages are relative to their respective ground.
Output supply current values are with no output load present. See Figure 4 and Figure 5 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
Because the input thresholds of the ADuM3100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse-width
Pulse-width distortion change vs. temperature is the absolute value of the change in pulse-width distortion for a 1°C change in operating temperature.
CM
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
PHL
PSK1
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 and Figure 5 for information on
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Input Dynamic Supply Current per Channel
Output Dynamic Supply Current per Channel
Change vs. Temperature
Propagation Delay Skew (Equal Temperature)
Propagation Delay Skew (Equal Temperature,
H
is measured from the 50% level of the falling edge of the V
is the magnitude of the worst-case difference in t
Supplies)
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
Logic Low/High Output
6, 8
I
signal to the 50% level of the rising edge of the V
7
9
PSK2
is the magnitude of the worst-case difference in t
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
10
PHL
10
6, 8
and/or t
I
signal to the 50% level of the falling edge of the V
Symbol
t
t
t
|CM
I
I
PLH
DDI (D)
DDO (D)
PSK1
PSK2
R
, t
that is measured between units at the same operating temperature and output load within the
f
L
O
|, |CM
signal.
Rev. A | Page 6 of 16
H
|
Min
25
PHL
and/or t
Typ
3
10
35
0.09
0.08
0.01
0.02
3
O
> 0.8 V
PLH
that is measured between units at the same operating
DD2
Max
12
15
9
12
. CM
O
L
is the maximum common-mode voltage slew rate
signal. t
Unit
ps/ºC
ps/ºC
ns
ns
ns
ns
ns
kV/μs
mA/Mbps
mA/Mbps
mA/Mbps
mA/Mbps
PLH
is measured from the 50% level of the
Test Conditions
C
C
C
C
C
C
C
V
transient magnitude = 800 V
I
L
L
L
L
L
L
L
= 0 or V
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
DD1
, V
CM
= 1000 V,