ox16c954 ETC-unknow, ox16c954 Datasheet - Page 26

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

interrupt causes IRQ# to be asserted.
LSR[6]: Transmitter and THR empty
logic 0
logic 1
LSR[7]: Receiver data error
logic 0
10 I
In Intel mode, the serial channel interrupts are asserted on
the respective INT pin. When INTSEL# is high the INT pin
is permanently enabled and MCR[3] is ignored. When
INTSEL# is low or unconnected, the tri-state control of INT
is controlled by MCR[3] (enabled when MCR[3] is set, high-
impedance state when MCR[3] is cleared).
In Motorola mode, all channel interrupts are ORed together
and asserted on the IRQ# pin. The INTSEL# pin has no
effect in this mode. The tri-state control of each channels
interrupt is controlled by MCR[3]. Any non-tristated channel
10.1 Interrupt Enable Register ‘IER’
Serial channel interrupts are enabled using the Interrupt
Enable Register (‘IER’).
IER[0]: Receiver data available interrupt mask
logic 0
logic 1
IER[1]: Transmitter empty interrupt mask
logic 0
logic 1
IER[2]: Receiver status interrupt
Normal mode:
logic 0
logic 1
9-bit data mode:
logic 0
logic 1
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
NTERRUPTS
The transmitter is not idle
THR is empty and the transmitter has
completed the character in shift register and is
in idle mode. (I.e. set whenever the transmitter
shift register and the THR are both empty.)
Either there are no receiver data errors in the
FIFO or it was cleared by an earlier read of
LSR.
Disable the receiver ready interrupt.
Enable the receiver ready interrupt.
Disable the transmitter empty interrupt.
Enable the transmitter empty interrupt.
Disable the receiver status interrupt.
Enable the receiver status interrupt.
Disable receiver status and address bit
interrupt.
Enable receiver status and address bit
interrupt.
& S
LEEP
M
ODE
logic 1
In 450 mode LSR[7] is permanently cleared, otherwise this
bit will be set when an erroneous character is transferred
from the receiver to the RHR. It is cleared when the LSR is
read. Note that in 16C550 this bit is only cleared when
all of the erroneous data are removed from the FIFO. In
9-bit data framing mode parity is permanently disabled, so
this bit is not affected by LSR[2].
In 9-bit mode (i.e. when NMR[0] is set), reception of a
character with the address-bit (i.e. 9
a level 1 interrupt if IER[2] is set.
IER[3]: Modem status interrupt mask
logic 0
logic 1
IER[4]: Sleep mode
logic 0
logic 1
Sleep mode is described in section 10.4.
IER[5]: Special character interrupt mask or alternate
sleep mode
9-bit data framing mode:
logic 0
logic 1
In 9-bit data mode, The receiver can detect up to four
special characters programmed in the Special Character
Registers (see map on page 19). When IER[5] is set, a
level 5 interrupt is asserted when the receiver character
matches one of the values programmed.
650/950 modes (non-9-bit data framing):
logic 0
logic 1
In 16C650 compatible mode when the device is in
Enhanced mode (EFR[4]=1), this bit enables the detection
of special characters. It enables both the detection of
XOFF characters (when in-band flow control is enabled via
EFR[3:0]) and the detection of the XOFF2 special
character (when enabled via EFR[5]).
At least one parity error, framing error or break
indication in the FIFO.
Disable the modem status interrupt.
Enable the modem status interrupt.
Disable sleep mode.
Enable sleep mode whereby the internal clock
of the channel is switched off.
Disable the received special character interrupt.
Enable the received special character interrupt.
Disable the special character receive interrupt.
Enable the special character receive interrupt.
th
OX16C954 rev B
bit) set can generate
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