ox16c954 ETC-unknow, ox16c954 Datasheet - Page 46
ox16c954
Manufacturer Part Number
ox16c954
Description
High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
Manufacturer
ETC-unknow
Datasheet
1.OX16C954.pdf
(54 pages)
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18 AC E
18.1 5V Operation
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
LECTRICAL
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
srww
hrww
t
t
t
t
t
t
t
t
t
t
t
srwr
hrwr
dw1
dw2
t
hdw
t
t
acc
t
acc
t
dr1
dr2
dhr
ha
hd
w1
w2
hd
ha
sa
sc
hc
sd
sa
sd
r1
r2
fd
fd
Parameter
Address set-up time to IOR# or IOW# falling
Address hold time after IOR# or IOW# rising
Chip-select set-up time to IOR# or IOW# falling
Chip-select hold time after IOR# or IOW# rising
Pulse duration of IOR#
Delay time between IOR# rising and IOR# or IOW# falling
Data valid after IOR# falling (access time)
Data valid (hold) after IOR# rising
Data bus floating after IOR# rising
Pulse duration of IOW#
Delay time between IOW# rising and IOR# or IOW# falling
Data set-up time to IOW# rising
Data hold time after IOW# rising
Parameter
Address set-up time to DS# falling
Address hold time after DS# rising
R/W# set-up time to DS# falling (read cycle)
R/W# hold time after DS# rising (read cycle)
Pulse duration of DS# (read cycle)
Delay to start of next read/write cycle (read cycle)
Read data valid after DS# falling (access time)
Read data hold data after DS# rising
Data bus float after DS# rising
R/W# set-up time to DS# falling (write cycle)
R/W# hold time after DS# rising (write cycle)
Pulse duration of DS# (write cycle)
Delay to start of next read/write cycle (write cycle)
Write data set-up time to DS# rising
Write data valid after DS# rising
C
HARACTERISTICS
Table 25: Data bus timing for Motorola mode:
Table 24: Data bus timing for Intel mode
Min
Min
29
43
29
43
29
43
29
43
0
0
0
0
0
0
4
5
0
5
0
0
5
0
0
4
Max
Max
23
10
23
10
OX16C954 rev B
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 46