ht82m9be Holtek Semiconductor Inc., ht82m9be Datasheet

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ht82m9be

Manufacturer Part Number
ht82m9be
Description
Ht82m99e/ht82m99a -- Usb Mouse Encoder 8-bit Mcu
Manufacturer
Holtek Semiconductor Inc.
Datasheet
Technical Document
Features
General Description
The USB MCU OTP body is suitable for USB mouse
and USB joystick devices. It consists of a Holtek high
performance 8-bit MCU core for control unit, built-in
USB SIE, 8K 16 ROM and 224 bytes data RAM.
Rev. 1.60
Tools Information
FAQs
Application Note
Flexible total solution for applications that combine
PS/2 and low-speed USB interface, such as mice,
joysticks, and many others
USB Specification Compliance
Supports 1 low-speed USB control endpoint and
3 interrupt endpoint
Each endpoint has 8 8 bytes FIFO
Integrated USB transceiver
3.3V regulator output
External 6MHz or 12MHz ceramic resonator or crystal
8-bit RISC microcontroller, with 8K 16 program
224 bytes RAM (20H~FFH)
6MHz/12MHz internal CPU clock
memory (0000H~1FFFH)
Conforms to USB specification V2.0
Conforms to USB HID specification V2.0
USB Mouse Encoder 8-Bit MCU
1
HT82M9BE/HT82M9BA
The mask version HT82M9BA is fully pin and functionally
compatible with the OTP version HT82M9BE device.
8-level stacks
Two 8-bit indirect addressing registers
One 8-bit programmable timer counter with overflow
interrupt (shared with PA6, vector 08H)
One 16-bit programmable timer counter with
overflow interrupt (shared with PA7, vector 0CH)
One USB interrupt input (vector 04H)
HALT function and wake-up feature reduce power
consumption
PA0~PA7, PB4 and PB7 support wake-up function
Internal Power-On reset (POR)
Watchdog Timer (WDT)
20 I/O ports
24/28-pin SSOP (209mil) package
32-pin QFN package
April 16, 2008

Related parts for ht82m9be

ht82m9be Summary of contents

Page 1

... HALT function and wake-up feature reduce power consumption PA0~PA7, PB4 and PB7 support wake-up function Internal Power-On reset (POR) Watchdog Timer (WDT) 20 I/O ports 24/28-pin SSOP (209mil) package 32-pin QFN package The mask version HT82M9BA is fully pin and functionally compatible with the OTP version HT82M9BE device. 1 April 16, 2008 ...

Page 2

... Block Diagram Pin Assignment Rev. 1.60 HT82M9BE/HT82M9BA 2 April 16, 2008 ...

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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.60 HT82M9BE/HT82M9BA Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is con- trolled by PAC (PA control register) ...

Page 4

... RES t System Start-up Timer Period SST t Crystal Setup OSC Note: Power-on period WDT SST OSC WDT Time-out in normal mode=1/f WDT Time-out in HALT mode=1/f Rev. 1.60 HT82M9BE/HT82M9BA Test Conditions V Conditions DD No load, f =6MHz 5V SYS No load, f =12MHz 5V SYS No load, system HALT, 5V USB suspend** ...

Page 5

... S12 S11 S10 Note: *12~*0: Program counter bits #12~#0: Instruction code bits Rev. 1.60 HT82M9BE/HT82M9BA After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. ...

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... TABRDL [ Note: *12~*0: Table location bits @7~@0: TBLP bits Rev. 1.60 HT82M9BE/HT82M9BA Table location Any location in the program memory can be used as look-up tables. There are three method to read the ROM data by two table read instructions: TABRDC and TABRDL , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H) ...

Page 7

... The RAM bank 1 mapping is as shown. Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers Rev. 1.60 HT82M9BE/HT82M9BA Bank 0 RAM Mapping Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...

Page 8

... Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions. The ALU provides the following functions: Rev. 1.60 HT82M9BE/HT82M9BA Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, OR, XOR, CPL) Rotation (RL, RR, RLC, RRC) Increment and Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ ...

Page 9

... The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO of the HT82M9BE/ HT82M9BA, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed ...

Page 10

... OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The HT82M9BE/HT82M9BA can operate in 6MHz or 12MHz system clocks. In order to make sure that the USB SIE functions properly, user should correctly con- figure the SCLKSEL bit of the SCC Register ...

Page 11

... All of the I/O ports remain in their original status. The PDF flag is set and the TO flag is cleared. Rev. 1.60 HT82M9BE/HT82M9BA The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig- nal on port WDT overflow. An external reset causes a device initialization and the WDT overflow per- forms a warm reset ...

Page 12

... WDTS 1000 0111 1000 0111 STATUS --00 xxxx --1u uuuu INTC -000 0000 -000 0000 TMR0 xxxx xxxx 0000 0000 Rev. 1.60 HT82M9BE/HT82M9BA Reset Circuit Reset Timing Chart Reset Configuration RES Reset WDT RES Reset (Normal Time-out (HALT) Operation) (HALT)* 000H 000H ...

Page 13

... Using the internal clock source, there is only 1 reference time-base for Timer/Event Counter 0. The internal clock source is coming from f /4. SYS Rev. 1.60 HT82M9BE/HT82M9BA RES Reset WDT RES Reset (Normal Time-out (HALT) Operation) (HALT)* ...

Page 14

... TM1 11=Pulse width measurement mode 00=Unused Rev. 1.60 HT82M9BE/HT82M9BA In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR0/TMR1 has re- ceived a transient from low to high (or high to low if the TE bits will start counting until the TMR0/TMR1 returns to the original level and resets the TON. The measured result will remain in the Timer/Event Counter 0/1 even if the activated transient occurs again ...

Page 15

... PA to PC, which are mapped to the data memory of [12H], [14H] and [16H] respectively. All of these I/O ports can be used for input Rev. 1.60 HT82M9BE/HT82M9BA Timer/Event Counter 0 Timer/Event Counter 1 and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 16H) ...

Page 16

... A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.60 HT82M9BE/HT82M9BA Low Voltage Reset - LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device drops to within the range of 0 ...

Page 17

... Bit7~Bit4 R/W Name Address Reserved Pipe_ctrl R/W 01000001B STALL R/W 01000011B Endpt_EN R/W 01000111B Pipe_ctrl (41H), STALL (43H) and Endpt_EN (47H) Registers Rev. 1.60 HT82M9BE/HT82M9BA SIES MISC Endpt_EN FIFO0 45H 46H 47H 48H Register Memory Mapping Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Address value Default value=00000000 Bit 3 ...

Page 18

... End of transient flag, normal status suspend= 1 line & EOT= 0 indicates that EOT R something is wrong in the USB Interface. The programmer must do something to save the device and keep it alive. MNI R/W This bit is for masking the NAK interrupt when MNI the default value= 0 Rev. 1.60 HT82M9BE/HT82M9BA Read/Write MNI R/W EOT R R/W NAK R ...

Page 19

... FIFO pointer register (FIFO0, FIFO1, FIFO2, FIFO3). The following are two examples for reading and writing the FIFO data: HT82M9BE/HT82M9BA FIFO is read by packet. To read from FIFO, the following should be followed: Select one set of FIFO, set in the read mode (MISC TX bit = 0), and set the REQ bit to 1 ...

Page 20

... USB interrupt is triggered. The follow- ing is the timing diagram: The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receive the wake-up signal from the HT82M9BE/HT82M9BA, it will 20 Bit7~Bit0 Data7~Data0 Data7~Data0 ...

Page 21

... Resume signal to the device. The timing is as fol- lows: To Configure the device as PS2 Device The HT82M9BE/HT82M9BA can be defined as a USB interface or a PS2 interface by configuring the SPS2 (bit 4 of the USR) and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0, the HT82M9BE/HT82M9BA is defined as ...

Page 22

... PEC4 R/W 5 PEC5 R/W 6 PEC6 R/W 7 PEC7 R/W Rev. 1.60 HT82M9BE/HT82M9BA Option Functions I/O (R/W), has pull-high option Reserved PC (16H) Register Option Functions USB suspend mode status bit. When 1, indicates that the USB SUSPEND system entry is in suspend mode. RMOT_WK USB remote wake-up signal. The default value ...

Page 23

... CLR WDT , instructions 10 TBHP enable/disable (default: disable output mode (CMOS/NMOS/PMOS) by bit (default: CMOS) Rev. 1.60 HT82M9BE/HT82M9BA Option Functions Reserved, must set USB clock control bit. When set indicates a USBCK ON, USBCKEN else USBCK OFF. The default value This bit is used to reduce power consumption in the suspend mode ...

Page 24

... RES high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 1.60 HT82M9BE/HT82M9BA 24 April 16, 2008 ...

Page 25

... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.60 HT82M9BE/HT82M9BA Description 25 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...

Page 26

... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.60 HT82M9BE/HT82M9BA Description 26 Instruction Flag Cycle Affected 2 ...

Page 27

... ACC+x Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF PDF PDF ...

Page 28

... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF PDF addr PDF OV Z ...

Page 29

... Affected flag( CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF PDF OV ...

Page 30

... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...

Page 31

... Operation Program Counter Affected flag(s) TO MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA Program Counter+1 PDF PDF PDF ...

Page 32

... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF Program Counter+1 ...

Page 33

... Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA Stack PDF Stack PDF ...

Page 34

... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...

Page 35

... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF OV Z ...

Page 36

... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF ...

Page 37

... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF PDF ...

Page 38

... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF PDF ...

Page 39

... XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.60 HT82M9BE/HT82M9BA PDF PDF PDF OV ...

Page 40

... Package Information 24-pin SSOP (209mil) Outline Dimensions Symbol Rev. 1.60 HT82M9BE/HT82M9BA Dimensions in mil Min. Nom. 291 196 9 311 Max. 323 220 15 345 April 16, 2008 ...

Page 41

... SSOP (209mil) Outline Dimensions Symbol Rev. 1.60 HT82M9BE/HT82M9BA Dimensions in mil Min. Nom. 291 196 9 396 65 25. Max. 323 220 15 407 April 16, 2008 ...

Page 42

... SAW Type QFN Outline Dimensions Symbol Rev. 1.60 HT82M9BE/HT82M9BA Dimensions in mm. Min. Nom. 0.7 0 0.2 0. 0.5 1.25 1.25 0.3 42 Max. 0.8 0.05 0.3 3.25 3.25 0.5 April 16, 2008 ...

Page 43

... Product Tape and Reel Specifications Reel Dimensions SAW QFN 32 (5 5mm) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.60 HT82M9BE/HT82M9BA Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 12.5+0.3 0.2 43 April 16, 2008 ...

Page 44

... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.60 HT82M9BE/HT82M9BA Dimensions 0.3 8 0.1 1.75 0.1 5.5 0.05 1.5+0.1 1.5+0.25 4 0.1 2 0.05 5.25 0.1 5.25 0.1 1.1 0.1 0.3 0.05 44 April 16, 2008 ...

Page 45

... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.60 HT82M9BE/HT82M9BA 45 April 16, 2008 ...

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