ht82m9be Holtek Semiconductor Inc., ht82m9be Datasheet - Page 11

• Manufacturer Part Number: ht82m9be
• Description: Ht82m99e/ht82m99a -- Usb Mouse Encoder 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

logic. The high nibble and bit 3 of the WDTS are re-
served for user defined flags, which can only be set to
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-
ommended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset
and only the program counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a HALT in-
struction. The software instruction include CLR WDT
and the other set
these two types of instruction, only one can be active de-
pending on the ROM code option
lection option . If the CLR WDT is selected (i.e.
CLRWDT times is equal to one), any execution of the
that CLR WDT and CLR WDT are chosen (i.e.
CLRWDT times is equal to two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
Rev. 1.60
10000 (WDTS.7~WDTS.3).
CLR WDT instruction will clear the WDT. In the case
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on-chip RAM and registers remain
unchanged.
The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports remain in their original status.
The PDF flag is set and the TO flag is cleared.
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WDTS (09H) Register
CLR WDT1 and CLR WDT2 . Of
WS0
0
1
0
1
0
1
0
1
Division Ratio
CLR WDT times se-
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8
11
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-
cuting the CLR WDT instruction and is set when exe-
cuting the HALT instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP; the others remain in
their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the inter-
rupt is enabled but the stack is full, the program will re-
sume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are four ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the program counterand SP, leaving
the other circuits in their original state. Some registers
remain unchanged during other reset conditions. Most
registers are reset to the initial condition when the re-
set conditions are met. By examining the PDF and TO
flags, the program can distinguish between different
1 before entering the HALT mode, the wake-up func-
chip resets .
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
USB reset
HT82M9BE/HT82M9BA
SYS
April 16, 2008
(system clock