ht82k70e-l Holtek Semiconductor Inc., ht82k70e-l Datasheet - Page 22

• Manufacturer Part Number: ht82k70e-l
• Description: I/o Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Interrupts
Interrupts are an important part of any microcontroller
system. When an external interrupt pin transition or two
internal function such as a Timer/Event Counter over-
flow, a transmission or reception of SPI data occurs,
their corresponding interrupt will enforce a temporary
suspension of the main program allowing the
microcontroller to direct attention to their respective
needs. Each device contains one external interrupts
and several internal interrupts functions. The external
interrupt is controlled by the action of the external inter-
rupt pins, while the internal interrupts are controlled by
the Timer/Event Counter overflow and SPI data trans-
mission or reception.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by the two inter-
rupt control registers, which are located in the Data
Memory. By controlling the appropriate enable bits in
these registers each individual interrupt can be enabled
or disabled. Also when an interrupt occurs, the corre-
sponding request flag will be set by the microcontroller.
The global enable flag if cleared to zero will disable all
interrupts.
Interrupt Operation
Two Timer/Event Counter overflow, 16-bits of data
transmission or reception on either of the one SPI inter-
faces or an active edge on any of the one external inter-
rupt pins will all generate an interrupt request by setting
their corresponding request flag, if their appropriate in-
terrupt enable bit is set. When this happens, the Pro-
gram Counter, which stores the address of the next
instruction to be executed, will be transferred onto the
stack. The Program Counter will then be loaded with a
new address which will be the value of the correspond-
ing interrupt vector. The microcontroller will then fetch its
next instruction from this interrupt vector. The instruction
at this vector will usually be a JMP statement which will
jump to another section of program which is known as
the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
Rev. 1.00
22
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the accompanying
diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
External Interrupt INT
Timer/Event Counter 0
Overflow Interrupt
Timer/Event Counter 1
Overflow Interrupt
SPI Interrupt
Interrupt Source
HT82K70E-L/HT82K76E-L
Priority
1
2
3
4
September 15, 2009
000CH
Vector
0004H
0008H
0010H