ht82k70e-l Holtek Semiconductor Inc., ht82k70e-l Datasheet - Page 24

• Manufacturer Part Number: ht82k70e-l
• Description: I/o Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

External Interrupt
For an external interrupt to occur, the global interrupt en-
able bit, EMI, and external interrupt enable bit, EEI must
first be set. An actual external interrupt will take place
when the external interrupt request flag, EIF is set, a sit-
uation that will occur when a high to low transition ap-
pears on the interrupt pins. The external interrupt pin is
pin-shared with the I/O pins PC2 can only be configured
as an external interrupt pin if the corresponding external
interrupt enable bits in the interrupt control register
INTC0 have been set. The pins must also be setup as
inputs by setting the corresponding PCC.2 bits in the
port control register. When the interrupt is enabled, the
stack is not full and a high to low transition appears on
the external interrupt pin, a subroutine call to the exter-
nal interrupt vector at location 04H will take place. When
the interrupt is serviced, the external interrupt request
flag, EIF will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts.
Note that any pull-high resistor configuration options on
these pins will remain valid even if the pins are used as
external interrupt inputs.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I or ET1I, must first be set. An
actual Timer/Event Counter interrupt will take place
when the Timer/Event Counter interrupt request flag,
T0F or T1F, is set, a situation that will occur when the
Timer/Event Counter overflows. When the interrupt is
enabled, the stack is not full and a Timer/Event Counter
overflow occurs, a subroutine call to the timer interrupt
vector at location 08H or 0CH, will take place. When the
interrupt is serviced, the timer interrupt request flag, T0F
or T1F, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts.
SPI Interrupt
For an SPI Interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding SPI interrupt enable bit,
Rev. 1.00
24
ESII, must be first set. The SBEN bit in the SBCR regis-
ter must also be set. An actual SPI Interrupt will take
place when one of the one SPI interrupt request flags,
SIF, is set, a situation that will occur when 8-bits of data
are transferred or received from either of the SPI inter-
faces. When the interrupt is enabled, the stack is not full
and an SPI interrupt occurs, a subroutine call to the SPI
interrupt vector at location 10H, will take place. When
the interrupt is serviced, the SPI interrupt request flag,
SIF, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts.
Programming Considerations
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt control register until the corre-
sponding interrupt is serviced or until the request flag is
cleared by a software instruction.
It is recommended that programs do not use the CALL
subroutine instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well con-
trolled, the original control sequence will be damaged
once a CALL subroutine is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
Only the Program Counter is pushed onto the stack. If
the contents of the accumulator or status register are al-
tered by the interrupt service program, which may cor-
rupt the desired control sequence, then the contents
should be saved in advance.
HT82K70E-L/HT82K76E-L
September 15, 2009