ht82d20r Holtek Semiconductor Inc., ht82d20r Datasheet
ht82d20r
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ht82d20r Summary of contents
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... Wireless system. Flexible total solution for applications that combine PS/2 and low-speed USB interface and 27MHz wireless system, such as mice, joysticks, and many others. Rev. 1.00 HT82D20R/HT82D20A 27MHz One Channel RX 8-Bit MCU 8-bit RISC microcontroller, with 2K 14 bits EPROM (000H~7FFH) 96 bytes RAM (20H~7FH) ...
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... Block Diagram Pin Assignment Rev. 1.00 HT82D20R/HT82D20A 2 November 3, 2009 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 HT82D20R/HT82D20A Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by configuration option. The input or output mode is controlled by PAC (PA control register) ...
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... PH2 R Pull-high Resistance for PA0~PA7 PH3 V Low Voltage Reset LVR Note: * The DATA pull-high is implemented using an external 1.5k resister. ** includes 15k load on the USBD+, USBD- line at the host terminal. Rev. 1.00 HT82D20R/HT82D20A Test Conditions Min. V Conditions DD 4.0 No load, f =12MHz 5V XTAL No load, system HALT, ...
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... Adjacent Channel Rejection REJ f Frequency Deviation DEV DR Data Rate FSK V Internal Mid-rail Reference REF1 V Internal Supply Voltage Reference 5V REF2 t Power Up Settling Time PU Rev. 1.00 HT82D20R/HT82D20A Test Conditions Min. V Conditions Without WDT prescaler 1024 75 Wake-up from HALT 256 WDTS+t RCSYS WDT 256 WDTS+t +t ...
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... Return from Subroutine S10 Note: *10~*0: Program counter bits #10~#0: Instruction code bits Rev. 1.00 HT82D20R/HT82D20A incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading to the PCL register, performing a sub- ...
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... ROM data as defined by TBLP and the current pro- gram counter bits. Table Location * Table Location P10~P8: Current program counter bits when TBHP is disabled TBHP register bit2~bit0 when TBHP is enabled 7 HT82D20R/HT82D20A * November 3, 2009 ...
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... Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i . They are also indirectly accessible through memory pointer registers (MP0 or MP1). Rev. 1.00 HT82D20R/HT82D20A Bank 0 RAM Mapping 8 November 3, 2009 ...
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... Address 00H~1FH in RAM Bank0 and Bank1 are lo- cated in the same Registers Bank 1 RAM Mapping Rev. 1.00 HT82D20R/HT82D20A Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters (IAR0:00H; IAR1:02H) that are not physically imple- mented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...
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... TF Internal timer/event counter request flag (1:active; 0:inactive) 7 Unused bit, read as 0 Rev. 1.00 HT82D20R/HT82D20A Function Status (0AH) Register Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded ...
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... USB interrupt 1 Timer/Event Counter overflow 2 Rev. 1.00 HT82D20R/HT82D20A Once the interrupt request flags (TF, USBF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts of- ten occur in an unpredictable manner or need to be ser- viced immediately in some applications ...
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... If the interrupt is enabled and the stack is not full, the regular interrupt re- sponse takes place interrupt request flag is set to 1 before entering the HALT mode, the wake-up func- 12 HT82D20R/HT82D20A CLR WDT times November 3, 2009 ...
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... The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler WDT Timer/event Counter Off Input/output Ports Stack Pointer Reset Timing Chart Reset Configuration 13 HT82D20R/HT82D20A 000H Disable Clear Clear. After master reset, WDT begins counting Input mode Points to the top of the stack November 3, 2009 ...
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... FIFO0 xxxx xxxx uuuu uuuu FIFO1 xxxx xxxx uuuu uuuu Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.00 HT82D20R/HT82D20A RES Reset WDT RES Reset (Normal Time-Out (HALT) Operation) (HALT)* 0000 0000 0000 0000 uuuu uuuu ...
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... TM1 11=Pulse width measurement mode 00=Unused Rev. 1.00 HT82D20R/HT82D20A which means that the clock source comes from an exter- nal (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the f (Timer). The pulse width measurement mode can be used to count the high or low level duration of the exter- nal signal (TMR) ...
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... To function as an input, the corresponding latch of the con- Rev. 1.00 HT82D20R/HT82D20A trol register must write The input source also de- pends on the control register. If the control register bit the input will read the pad state. If the control regis- ter bit the contents of the latches will move to the int er nal bus ...
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... Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.00 HT82D20R/HT82D20A The relationship between V ) must LVR ...
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... The SIES Register is used to indicate the present signal state which the USB SIE received and also determines whether the USB SIE has to change the device address automatically. Bit No. Function 7 MNI 6~2 Reserved bit 1 F0_ERR 0 Adr_set Rev. 1.00 HT82D20R/HT82D20A STALL PIPE SIES MISC 43H 44H 45H Bank 1, Address 40H, 4AH, 4FH Register Memory Mapping Bit 5 Bit 4 Bit 3 ...
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... The MISC register is actually a command + status to control the desired FIFO action and to show the status of the de- sired FIFO. Every bit s meaning and usage are listed as follows: Bit No. Function 7 Len0 6 Ready 5 Set CMD 4 Sel_pipe1 3 Sel_pipe0 2 Clear Request Rev. 1.00 HT82D20R/HT82D20A Description SIES Function Table Read/Write R/W R R/W R/W R/W R/W R/W R/W MISC (46H) Registers Table 19 Register Address 01000110B November 3, 2009 ...
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... User reads the data through the FIFO pointer register, user has to record the number of bytes to be read. The devices allow a maximum of 8 bytes of data in each packet. Rev. 1.00 HT82D20R/HT82D20A Description MISC Function Table The FIFO is written by packet. To write to FIFO, the fol- lowing should be followed: ...
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... USBCKEN (bit 3 of the SCC and clear the Rev. 1.00 HT82D20R/HT82D20A MISC Setting Flow and Status 00H 01H delay check 41H read* from FIFO0 register and check if not ready (01H) 03H 02H ...
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... FSK Receiver Control Register 2 (15H) Bit2~bit4 & bit7 must the other bits are reserved Rev. 1.00 HT82D20R/HT82D20A The user should make sure that in order to read the data properly, the corresponding output bit must be set For example, if user wants to read the PS2 Data by reading PS2DAI, the PS2DAO should be set to 1 ...
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... R USBD-/DATA input R USBD+/CLK input Output for driving USBD-/DATA pin, when working under 3D PS2 W mouse function. Default value is 1. Output for driving USBD-/DATA pin, when working under 3D PS2 W mouse function. Default value HT82D20R/HT82D20A November 3, 2009 ...
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... LVR with no function. In the USB mode this bit cannot be set high. R/W Reserved R/W Reserved bit, set to 1 This flag is used to show that the MCU is in PS2 mode (Bit=1). This bit is R and will be cleared to zero after power-on reset. R/W The default value HT82D20R/HT82D20A November 3, 2009 ...
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... Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Components with * are used for EMC issue. Rev. 1.00 Functions R Store current table read bit10~bit8 data Option /4 (default: f /4) SYS 25 HT82D20R/HT82D20A November 3, 2009 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.00 HT82D20R/HT82D20A subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.00 HT82D20R/HT82D20A Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT82D20R/HT82D20A Description 28 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 HT82D20R/HT82D20A 29 November 3, 2009 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 HT82D20R/HT82D20A addr 30 November 3, 2009 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82D20R/HT82D20A November 3, 2009 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 HT82D20R/HT82D20A addr 32 November 3, 2009 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 33 HT82D20R/HT82D20A November 3, 2009 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 34 HT82D20R/HT82D20A November 3, 2009 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT82D20R/HT82D20A November 3, 2009 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT82D20R/HT82D20A November 3, 2009 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 HT82D20R/HT82D20A [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 37 November 3, 2009 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 HT82D20R/HT82D20A 38 November 3, 2009 ...
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... Package Information 28-pin SSOP (150mil) Outline Dimensions Symbol Rev. 1.00 HT82D20R/HT82D20A Dimensions in mil Min. Nom. 228 150 8 386 Max. 244 157 12 394 November 3, 2009 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 28S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 HT82D20R/HT82D20A Dimensions in mm 330.0 1.0 62.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 40 November 3, 2009 ...
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... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT82D20R/HT82D20A Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.30 0.05 13.3 0.1 41 November 3, 2009 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT82D20R/HT82D20A 42 November 3, 2009 ...