ht82d20r Holtek Semiconductor Inc., ht82d20r Datasheet - Page 20

• Manufacturer Part Number: ht82d20r
• Description: 27mhz One Channel Rx 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

The devices have two 8 8 bidirectional FIFO for the two
endpoints (control and Interrupt). User can easily
read/write the FIFO data by accessing the correspond-
ing FIFO pointer register (FIFO0, FIFO1). The following
are two examples for reading and writing the FIFO data:
The FIFO is read by packet. To read from FIFO, the fol-
lowing should be followed:
User reads the data through the FIFO pointer register,
user has to record the number of bytes to be read. The
devices allow a maximum of 8 bytes of data in each
packet.
Rev. 1.00
Request
Tx
Clear
Sel_pipe1
Sel_pipe0
Set CMD
Ready
Len0
Select one set of FIFO, set in the read mode (MISC
TX bit = 0), and set the REQ bit to 1 .
Check the ready bit until the status = 1
Read through the FIFO pointer register, and record
the data number that has been read.
Repeat steps 2 and 3 until the ready bit becomes 0
which indicates the end of the FIFO data reading.
Set MISC TX bit = 1
Clear the REQ bit to 0. Complete reading.
Function
Name
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
After setting the other desired status, FIFO can be requested by setting this bit high active.
After work has been done, this bit must be set low.
Represents the direction and transition end of the MCU accesses. When being set as logic
1, the MCU wants to write data to FIFO. After work has been done, this bit must be set to
logic 0 before terminating the request to represent a transition end. For reading action, this
bit must be set to logic 0 to indicate that the MCU wants to read and must be set to logic 1
after work is done.
Represents MCU clear requested FIFO, even if FIFO is not ready.
Determines which FIFO is desired, 00 for FIFO 0, 01 for FIFO 1
Shows that the data in FIFO is setup as command. This bit will be cleared by firmware. So,
even if the MCU is busy, nothing is missed by the SETUP command from the host.
Indicates that the desired FIFO is ready to work.
Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a
read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after
the next valid SETUP token is received.
MISC Function Table
20
The FIFO is written by packet. To write to FIFO, the fol-
lowing should be followed:
User writes the data through the FIFO pointer register,
user has to record the number of bytes that have been
written. The devices allow a maximum of 8 bytes of data
in each packet.
Select a set of FIFO, set in the write mode (MISC TX
bit = 1), and set the REQ bit to 1
Check the ready bit until the status = 1
Write through the FIFO pointer register and take down
the data number that has been written
Repeat steps 2 and 3 until writing is complete or the
ready bit becomes 0 which indicates that the FIFO no
longer allows any data writing.
Set MISC TX bit = 0
Clear the REQ bit to 0. Complete writing.
Description
HT82D20R/HT82D20A
November 3, 2009