gal20v8b-15lr-883 Lattice Semiconductor Corp., gal20v8b-15lr-883 Datasheet - Page 5

• Manufacturer Part Number: gal20v8b-15lr-883
• Description: High Performance E2 Cmos Pld Generic Array Logic? Gal
• Manufacturer: Lattice Semiconductor Corp.

3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Note: fmax with external feedback is calculated from measured
tsu and tco.
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
fmax Descriptions
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
f
max with External Feedback 1/(
LOGIC
ARRAY
t
LOGIC
ARRAY
su +
f
max with No Feedback
t
t
su
h
390Ω
390Ω
390Ω
R
∞
∞
1
REGISTER
REGISTER
CLK
CLK
750Ω
750Ω
750Ω
750Ω
750Ω
R
3ns 10% – 90%
2
t
GND to 3.0V
t
co
See Figure
su+
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
5
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
Specifications GAL20V8/883
FROM OUTPUT (O/Q)
UNDER TEST
*C
f
L
max with Internal Feedback 1/(
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
LOGIC
ARRAY
R
2
+5V
t
cf
t
pd
REGISTER
R
1
CLK
C *
t
L
su+
TEST POINT
t
cf)