gal22lv10z Lattice Semiconductor Corp., gal22lv10z Datasheet - Page 12

• Manufacturer Part Number: gal22lv10z
• Description: Low Voltage, Zero Power E2 Cmos Pld
• Manufacturer: Lattice Semiconductor Corp.

An electronic signature (ES) is provided in every GAL22LV10Z and
GAL22LV10ZD device. It contains 64 bits of reprogrammable
memory that can contain user-defined data. Some uses include
user ID codes, revision numbers, or inventory control. The signature
data is always available to the user independent of the state of the
security cell.
The electronic signature is an additional feature not present in other
manufacturers’ 22V10 devices. To use the extra feature of the user-
programmable electronic signature it is necessary to choose a
Lattice Semiconductor 22LV10 device type when compiling a set
of logic equations. In addition, many device programmers have two
separate selections for the device, typically a GAL22LV10 and a
GAL22LV10-UES (UES = User Electronic Signature). This allows
users to maintain compatibility with existing 22V10 designs, while
still having the option to use the GAL device's extra feature.
The JEDEC map for the GAL22LV10Z and GAL22LV10ZD contains
the 64 extra fuses for the electronic signature, for a total of 5892
fuses. However, GAL22LV10Z and GAL22LV10ZD devices can still
be programmed with a standard 22V10 JEDEC map (5828 fuses)
with any qualified device programmer.
A security cell is provided in every GAL22LV10Z and
GAL22LV10ZD device to prevent unauthorized copying of the array
patterns. Once programmed, this cell prevents further read access
to the functional bits in the device. This cell can only be erased by
re-programming the device, so the original configuration can never
be examined once this cell is programmed. The Electronic Sig-
nature is always available to the user, regardless of the state of this
control cell.
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.
Electronic Signature
Security Cell
Device Programming
12
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
GAL22LV10Z and GAL22LV10ZD devices include circuitry that
allows each registered output to be synchronously set either high
or low. Thus, any present state condition can be forced for test
sequencing. If necessary, approved GAL programmers capable of
executing test vectors perform output register preload automati-
cally.
GAL22LV10Z and GAL22LV10ZD devices are designed with TTL
level compatible input buffers. These buffers have a characteris-
tically high impedance, and present a much lighter load to the
driving logic than bipolar TTL devices.
The GAL22LV10Z relies on its internal input transition detection cir-
cuitry to put the device into power down mode. If there is no input
transition for the specified period of time, the device will go into the
power down state. Transition detection on any input or I/O will put
the device back into the active state. Any input pulse widths greater
than 5ns at an input transition voltage level of 1.5V will be detected
as an input transition. The device will not detect input pulse widths
less than 1ns measured at an input transition voltage level of 1.5V
as an input transition.
The GAL22LV10ZD uses pin 5 as the dedicated power-down signal
to put the device into the standby state. DPP is an active high
signal. A logic high driven onto this signal puts the device into the
standby state. Input pin 5 cannot be used as a logic function in-
put on this device.
Output Register Preload
Input Buffers
Input Transition Detection (ITD)
Dedicated Power-Down Pin
Specifications GAL22LV10Z
GAL22LV10ZD