hn58x2508fpiag Renesas Electronics Corporation., hn58x2508fpiag Datasheet - Page 14

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hn58x2508fpiag

Manufacturer Part Number
hn58x2508fpiag
Description
Serial Peripheral Interface Electrically Erasable And Programmable Read Only Memory
Manufacturer
Renesas Electronics Corporation.
Datasheet
HN58X2508IAG Series, HN58X2516IAG Series
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an
internal address register, and the byte of data at that address is shifted out, on serial data output (Q).
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of
data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued
indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at
any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted,
and is not executed, if a Write cycle is currently in progress.
Read from Memory Array (READ) Sequence
Note:
Address Range Bits
Address bits
Notes: 1. b15-b11 are don’t care on the HN58X2516IAG
Rev.1.00, Nov.08.2006, page 14 of 20
W
C
D
Q
S
1. Depending on the memory size, as shown in the following table, the most significant address bits are don’t
2. b15-b10 are don’t care on the HN58X2508IAG
care.
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
Device
0
1
2
Instruction
3
4
A10 to A0
5
High-Z
6
7
A15
8
A14
HN58X2516IAG
9 10
16-Bit Address
A13
A3
20 21 22 23 24 25 26 27 28 29 30 31
A2
A1
A0
7
6
5
Data Out 1
A9 to A0
4
3
2
HN58X2508IAG
1
0
7
Data Out 2

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