as7c3364ntd32b Alliance Memory, Inc, as7c3364ntd32b Datasheet - Page 15

• Manufacturer Part Number: as7c3364ntd32b
• Description: 3.3v 32/36 Pipelined Sram With
• Manufacturer: Alliance Memory, Inc

AC test conditions
Notes
• Output Load: see Figure B,
• Input pulse level: VSS to 3V. See Figure A.
• Input rise and fall time (Measured at 0.3V and 2.7V): 1.0V/ns. See Figure A.
• Input and output timing reference levels: 1.5V.
1
2
3
4
5
4/28/05; v.1.3
except for
+3.0V
VSS
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C
This parameter is sampled and not 100% tested.
t
ature and voltage.
t
have stopped driving.
HZOE
HZCN
Figure A: Input waveform
10%
90%
is less than t
is a
t
LZC
‘no load’ parameter to indicate exactly when SRAM outputs
, t
LZOE
LZOE
; and t
, t
90%
HZOE
10%
HZC
, t
is less than t
HZC
see Figure C.
D
out
LZC
at any given temper-
Figure B: Output load (A)
Z
0
=50
Alliance Semiconductor
Ω
6
7
50
30 pF*
Ω
t
VIL
This is a synchronous device. All addresses must meet the specified
setup and hold times for all rising edges of CLK. All other synchronous
inputs must meet the setup and hold times with stable logic levels for all
rising edges of CLK when chip is enabled.
CH
®
V
measured as HIGH above VIH, and t
L
=1.5V
353Ω / 1538Ω
D
OUT
Figure C: Output load (B)
AS7C3364NTD32B
AS7C3364NTD36B
Thevenin equivalent:
319Ω / 1667Ω
5 pF*
GND
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
CL
measured as LOW below
*including scope
and jig capacitance
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