as7c251mntf18a Alliance Memory, Inc, as7c251mntf18a Datasheet - Page 15
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as7c251mntf18a
Manufacturer Part Number
as7c251mntf18a
Description
2.5v Flowthrough Synchronous Sram With
Manufacturer
Alliance Memory, Inc
Datasheet
1.AS7C251MNTF18A.pdf
(18 pages)
AC test conditions
Notes:
1) For test conditions, see “AC test conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
5) t
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to
8) Chip select refers to
12/23/04, v 1.1
HZOE
CH
• Output load: For t
• Input pulse level: GND to 2.5V. See Figure A.
• Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.25V.
+2.5V
GND
measured high above V
Figure A: Input waveform
10%
is less than t
90%
R/W and BW[a,b]
LZOE
CE0, CE1, and CE2
and t
LZC
Rising input
IH
, t
90%
HZC
and t
LZOE
.
10%
is less than t
CL
, t
.
measured as low below V
HZOE
D
OUT
, and t
LZC
at any given temperature and voltage.
Figure B: Output load (A)
HZC
, see Figure C. For all others, see Figure B.
Alliance Semiconductor
IL
Falling input
30 pF*
50Ω
V
L
®
= V
DDQ
/2
353Ω/1538Ω
D
OUT
Undefined/don’t care
Figure C: Output load(B)
AS7C251MNTF18A
Thevenin equivalent:
5 pF*
319Ω/1667Ω
GND
+2.5V
*including scope
and jig capacitance
P. 15 of 18