la-ispmach4032v Lattice Semiconductor Corp., la-ispmach4032v Datasheet - Page 6

• Manufacturer Part Number: la-ispmach4032v
• Description: 3.3v/1.8v In-system Programmable Superfast High Density Plds Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 5. Product Term Expansion Capability
Every time the super cluster allocator is used, there is an incremental delay of t
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
Expansion Chains
• Block CLK0
• Block CLK1
• Block CLK2
Single PT
Chain-0
Chain-1
Chain-2
Chain-3
PT Initialization/CE (optional)
PT Initialization (optional)
Shared PT Initialization
From Logic Allocator
Macrocells Associated with Expansion Chain (with Wrap Around)
PT Clock (optional)
Shared PT Clock
Block CLK0
Block CLK1
Block CLK2
Block CLK3
M2 → M6 → M10 → M14 → M2
M3 → M7 → M11 → M15 → M3
M0 → M4 → M8 → M12 → M0
M1 → M5 → M9 → M13 → M1
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Initialization
Power-up
6
Delay
D/T/L
CE
R
EXP
P
Q
. When the super cluster alloca-
Max PT/Macrocell
From I/O Cell
To ORP
To GRP
75
80
75
70