lc5256b-75t128i Lattice Semiconductor Corp., lc5256b-75t128i Datasheet - Page 6

• Manufacturer Part Number: lc5256b-75t128i
• Description: 2.5v In-system Programmable Superwide High Density Plds Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
each of these signals. The output of the OE MUX goes through a logical AND with the TOE signal to allow easy tri-
stating of the outputs for testing purposes.
The four Shared PTOE signals are derived from PT163 of each GLB. The PTOE signal is derived from the first
product term in each macrocell cluster, which is directly routed to the OE MUX. Therefore, every I/O cell can have a
different OE signal. Figure 6 is a graphical representation of the I/O cell.
Figure 6. ispMACH 5000B I/O Cell
sysIO Capability
The ispMACH 5000B devices are divided into four sysIO banks, where each bank is capable of supporting 14 dif-
ferent I/O standards. Each sysIO bank has its own I/O supply voltage (V
nation voltage (V
I/O within a bank is individually configurable consistent with the V
individually configurable drive strength, weak pull-up, weak pull-down or a bus-friendly latch. Table 2 lists the
sysIO standards with the typical values for V
The TOE and JTAG pins of the ispMACH 5000B device are the only pins that do not have sysIO capabilities. These
pins support the 2.5V LVTTL and LVCMOS standards.
There are three classes of I/O interface standards implemented in the ispMACH 5000B devices. The first is the
un-terminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V
LVCMOS interface standards. Additionally, PCI and AGP-1X are all subsets of this type of interface.
The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-
faces includes different versions of SSTL and HSTL interfaces along with CTT, GTL+ and single-ended LVPECL.
Use of these particular I/O interfaces requires an additional V
V
driving.
The final type of interfaces implemented are the differential standards LVDS and LVPECL. These interfaces are
implemented on clock pins only. When using one of the differential standards, a pair of global clock pins (GCLK0
and GCLK1 or GCLK2 and GCLK3) are combined to create a single clock signal.
TT
, is also required. Typically an output will be terminated to V
Global PTOE 0
Global PTOE 1
Global PTOE 2
Global PTOE 3
from Macrocell
TT
Data Output
, as applicable), resources allowing each bank complete independence from the others. Each
GOE0
GOE1
PTOE
TOE
Data Input to Macrocell
Data Input to Routing
CCO
, V
(V
REF
open drain outputs)
CCO
Output Buffer
and V
independent for
6
V
other I/Os
CCO
in bank
REF
TT
to all
TT
.
(V
CCO
REF
signal. At the system level a termination voltage,
at the receiving end of the transmission line it is
V
Input Buffer
CMOS/TTL
Input Buffer
REF
independent)
ispMACH 5000B Family Data Sheet
and V
dependent
CCO
), reference voltage (V
+
–
REF
whole chip
GND
V
settings. In addition, each I/O has
CC
V
other I/Os in bank
REF
for
to all
Pad
I/O
REF
), and termi-