ispgdx80va Lattice Semiconductor Corp., ispgdx80va Datasheet
ispgdx80va
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ispgdx80va Summary of contents
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... Copyright © 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com ...
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... I/Os. ** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and CLKEN3 respectively in all devices. Specifications ispGDX80VA In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs ...
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... I/O Cell 39 80 Input GRP 40 I/O Cells Inputs Vertical Outputs Horizontal Specifications ispGDX80VA The various I/O pin sets are also shown in the block diagram below. The and D I/O pins are grouped together with one group per side. I/O Architecture Each I/O cell contains a 4:1 dynamic MUX controlled by ...
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... MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard and D MUX inputs, and Specifications ispGDX80VA allow adjacent I/O cell outputs to be directly connected without passing through the global routing pool. The relationship between the [N+i] adjacent cells and ...
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... User-Programmable I/Os The ispGDX80VA features user-programmable Data C/ Data D/ I/Os supporting either 3.3V or 2.5V output voltage level MUXOUT MUXOUT options. The ispGDX80VA uses a VCCIO pin to provide B9 B8 the 2.5V reference voltage when used. B10 B9 PCI Compatible Drive Capability B11 B10 ...
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... Decoders Buffers / Registers Data Path System Bus #2 Clock(s) Specifications ispGDX80VA Programmable Switch Replacement (PSR) Includes solid-state replacement and integration of me- chanical DIP Switch and jumper functions. Through in-system programming, pins of the ispGDXVA devices can be driven to HIGH or LOW logic levels to emulate the traditional device outputs ...
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... OE3 Port #4 OE4 Note: All OE and SEL lines driven by external arbiter logic (not shown). Specifications ispGDX80VA Designing with the ispGDXVA As mentioned earlier, this architecture satisfies the PRSI class of applications without restrictions: any I/O pin as a single input or bidirectional can drive any other I/O pin as output ...
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... Supply Voltage CC V I/O Reference Voltage CCIO o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Dedicated Clock Capacitance 2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispGDX80VA 1 0°C to +70°C Commercial -40°C to +85°C Industrial A PACKAGE TYPE TYPICAL TQFP TQFP MINIMUM 10,000 8 MIN. MAX. 3.00 3.60 3 ...
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... CCIO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. Typical values are 3.3V and T CC Specifications ispGDX80VA Figure 8. Test Load GND to V CCIO(MIN) < 1.5ns 10 CCIO(MIN CCIO(MIN) Device See Figure 8 Output * 2. includes Test Fixture and Probe Capacitance ...
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... An input driving four I/O cells at 40MHz results in a dynamic I 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. Specifications ispGDX80VA Over Recommended Operating Conditions CONDITION – ...
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... I/O voltage reference. 3. The new “-3” speed grade (tpd = 3.0ns) will be effective starting with date code A113xxxx. Devices with topside date codes prior to A113xxxx adhere to the shaded “-3” speed grade (tpd = 3.5ns). Specifications ispGDX80VA Over Recommended Operating Conditions DESCRIPTION ...
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... Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. Specifications ispGDX80VA Over Recommended Operating Conditions DESCRIPTION 1 ...
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... External Timing Parameters (Continued) ispGDX80VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas ispGDX80VA Maximum Specifications ispGDX80VA apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder. ∆ ...
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... Internal Timing Parameters are not tested and are for reference only. 2. The new “-3” speed grade (tpd = 3.0ns) will be effective starting with date code A113xxxx. Devices with topside date codes prior to A113xxxx adhere to the shaded “-3” speed grade (tpd = 3.5ns). Specifications ispGDX80VA Over Recommended Operating Conditions 1 ...
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... Global Reset t 65 Global Reset to I/O Register Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX80VA 1 Over Recommended Operating Conditions 1 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — ...
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... Clock Width ispGDXVA Timing Model OE MUX Expander Input MUX0 MUX1 GRP tgrp #33 CLKEN tioclkeg #64 CLK tioclk #60 Y0,1,2,3 tgclk #61 Y0,1,2,3, Enable Specifications ispGDX80VA DATA (I/O INPUT) CLK REGISTERED I/O OUTPUT CLKEN t en RESET wl REGISTERED I/O OUTPUT tgoe #58 tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 MUX Expander Output tmuxcg #50 ...
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... TCK EPEN ispGDX 80VA Device Specifications ispGDX80VA are fed into the on-chip programming circuitry where a state machine controls the programming. On-chip programming can be accomplished using an IEEE 1149.1 boundary scan protocol. The IEEE 1149.1- compliant interface signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS) control ...
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... Clock DR Table 3. I/O Shift Register Order DEVICE TDI, TOE, RESET, Y1, Y0, I/O B10 .. B19, I C19, I D9, I B0, I/O A19.. A0, ispGDX80VA I/O D19 .. D10, TDO Table 4. ispGDX80VA Device ID Codes DEVICE 32-BIT BOUNDARY SCAN ID CODE ispGDX80VA 0001, 0000, 0011, 0101, 0000, 0000, 0100, 0011 Specifications ispGDX80VA allows customers using boundary scan test to have full test capability with only a single BSDL file ...
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... Input Pin SCANIN (from previous Shift DR Clock DR Figure 12. Boundary Scan State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 Specifications ispGDX80VA Downlowad software, ispCODE ‘C’ routines or any third- party programmers. Contact Lattice Technical Support to obtain more detailed programming information cell 1 1 Select-DR-Scan 0 ...
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... BSCAN test Capture register hold time t btuco BSCAN test Update reg, falling edge of clock to valid output t btuoz BSCAN test Update reg, falling edge of clock to output disable t btuov BSCAN test Update reg, falling edge of clock to output enable Specifications ispGDX80VA T T btsu bth T btcl ...
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... Input – This pin is used if optional 2.5V output used. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. Specifications ispGDX80VA Description 21 ...
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... Signal Locations: ispGDX80VA Signal 100-Pin TQFP RESET /I/O D10 90 Y0/CLKEN0 38 Y1/CLKEN1/TOE 87 EPEN 35 TDI 39 TCK 36 TMS 86 TDO 85 GND 6, 18, 29, 45, 56, 68, 79, 95 VCC 12, 37, 62, 88 VCCIO 89 I/O Locations: ispGDX80VA I/O Control 100 I/O Signal Signal TQFP Signal I/O A0 CLK 1 I I/O B2 I/O A2 MUXsel1 3 I/O B3 I/O A3 MUXsel2 4 I/O B4 I/O A4 CLK ...
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... Pin Configuration: ispGDX80VA ispGDX80VA 100-Pin TQFP Pinout Diagram Control Data CLK I I MUXsel1 I MUXsel2 I CLK I GND MUXsel1 I MUXsel2 I CLK I I VCC 12 I/O A10 13 MUXsel1 I/O A11 14 MUXsel2 I/O A12 15 CLK I/O A13 16 OE I/O A14 17 MUXsel1 GND ...
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... FAMILY tpd (ns) 5.0 ispGDXVA 7.0 9.0 Note: The ispGDX80VA devices are dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster, e.g. ispGDX80VA-3T100-5I. *The new “-3” speed grade (tpd = 3.0ns) will be effective starting with date code A113xxxx. Lead-Free Packaging FAMILY tpd (ns) 3 ...