ispgal22lv10 Lattice Semiconductor Corp., ispgal22lv10 Datasheet - Page 11

• Manufacturer Part Number: ispgal22lv10
• Description: In-system Programmable Low Voltage E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

Circuitry within the ispGAL22LV10 provides a reset signal to all
registers during power-up. All internal registers will have their
Q outputs set low after a specified time (tpr, 1 s MAX). As a
result, the state on the registered output pins (if they are
enabled) will be either high or low on power-up, depending on
the programmed polarity of the output pins. This feature can
greatly simplify state machine design by providing a known
state on power-up. The timing diagram for power-up is shown
above. Because of the asynchronous nature of system power-
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
(Vref = Vcc)
Input
Vcc
Active Pull-up Circuit
INTERNAL REGISTER
OUTPUT REGISTER
OUTPUT REGISTER
ACTIVE HIGH
Vref
ACTIVE LOW
Q - OUTPUT
C L K
V c c
Vcc
Vcc
Vcc (min.)
11
Specifications ispGAL22LV10
t
up, some conditions must be met to provide a valid power-up
reset of the ispGAL22LV10. First, the Vcc
monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will
reset within a maximum of tpr time. As in normal system
operation, avoid clocking the device until all input and feedback
path setup times have been met. The clock must also meet the
minimum pulse width requirements.
pr
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
t
wl
Feedback
Tri-State
Control
t
su
Vcc
Active Pull-up Circuit
Output
Feedback
(To Input Buffer)
Vref
(Vref = Vcc)
PIN
PIN
rise must be