ml70q5110la Oki Semiconductor, ml70q5110la Datasheet - Page 17

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ml70q5110la

Manufacturer Part Number
ml70q5110la
Description
Bluetooth Baseband Controller Ic
Manufacturer
Oki Semiconductor
Datasheet
External Memory
OKI Semiconductor
below.
[*1]
[*2]
Note: Oki software settings:
MCS0
MBS*
MWE
XA
MRE
(write)
(read)
XD_O
XD_I
ML70Q5110LA specifications for the devices that are connected to MCS0 and MCS1 are explained
When the device is connected to MCS0:
- 1 memory bank
- Bus width: 8 or 16 bits
- Byte access control: MBS*/MWE
- Supported devices:
Note: A device with an access time of 120 nsec or less is recommended.
Normal SRAM, Flash Memory, Page mode Flash memory
Access time:
3, 4, 5, 6, 7, 8 clock cycles (including 1 clock cycle for set-up)
6, 8, 10, 12, 14, 16 clock cycles (including 2 clock cycles for set-up)
Data OFF time:
1, 2, 3, 4 clock cycles
- Insert the maximum wait immediately after reset.
- Page mode: OFF
- During operation (32 MHz operation),
Access time: 3 clock cycles
Data OFF time: 1 clock cycle
clocks
1 or 2
Bus timing to the device connected to MCS0
[*1]
[*2]
17/26
1 or 2 clocks
[*1]
1 clock fixed
FEDL70Q5110LA-01
ML70Q5110LA

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