msm7503 Oki Semiconductor, msm7503 Datasheet

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msm7503

Manufacturer Part Number
msm7503
Description
Multi-function Pcm Codec
Manufacturer
Oki Semiconductor
Datasheet

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Part Number:
msm7503GS-BK
Manufacturer:
SIL
Quantity:
3 224
E2U0024-16-X2
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MSM7503
Multi-Function PCM CODEC
GENERAL DESCRIPTION
The MSM7503 is a high performance, low power CODEC LSI device integrating a 2-wire time
division transmission (ping-pong transmission) interface function and has a basic function of
man-machine interface to that of the MSM7502.
The MSM7503 operates from single 5 V power supply and is ideal for digital telephone terminals
such as pushbutton telephone sets and digital PBXs.
The MSM7503 ping-pong transmission interface supports a bidirectional communication of up
to 800 m long on the 2-wire twisted pair line, and can send and receive voice data at 64 kbps and
control data at 16 kbps.
The man-machine interface consists of analog speech path, key-scanner, tone generators,
CODEC meeting the m/A companding law, and processor interface, which are controlled via 8-
bit data buses.
FEATURES
• Single +5 V Power Supply
• Low Power Dissipation
• Pin-Pong Transmission
• Transmission data configuration
• Control Data Interface supports synchronous and asynchronous communications
• Built-in Power-on Reset by the power supply voltage monitoring
• Output of the ping-pong transmission monitoring signal
• CODEC complied by the ITU-T companding law
• Calling Tone Interval
• Calling Tone Combination
• Calling Tone Volume
• Ringing Tone Interval
• Ringing Tone Frequency
• Ringing Tone Level
• Built-in PB Tone Generator
• Built-in Speech path Control Switches
• General Latch Output for External Control : 2 bits
• Watch-dog Timer
Power ON Mode
Power Down Mode
: 50 mW Typ. 100 mW Max.
: 15 mW Typ. 30 mW Max.
: Burst of 8 kHz, Transmission of 256 kbps,
: Transmit Start bit (1 bit), K-bit (1 bit),
: Controlled by processor
: Controlled by processor, 6 modes
: Controlled by processor, 4 modes
: Controlled by processor
: Controlled by processor, 6 modes
: Controlled by processor, 4 levels
: 500 ms
AMI coding, 2-wire time division transmission
Receive
Control bit (2 bits), Voice bit (8 bits),
DC balance bit (1 bit), totalling 13 bits
Sync bit (4 bits), K-bit (1 bit),
Control bit (2 bits), Voice bit (8 bits),
DC balance bit (1 bit), totalling 16 bits
Previous version: Nov. 1996
This version: Jan. 1998
MSM7503
1/41

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msm7503 Summary of contents

Page 1

... MSM7502. The MSM7503 operates from single 5 V power supply and is ideal for digital telephone terminals such as pushbutton telephone sets and digital PBXs. The MSM7503 ping-pong transmission interface supports a bidirectional communication 800 m long on the 2-wire twisted pair line, and can send and receive voice data at 64 kbps and control data at 16 kbps ...

Page 2

... Input • Direct Connection to Handset • Built-in Pre-amplifier for Loud-speaker • Hand-free Interface • m-law/A-law Switchable CODEC • LCD Deflection Angle Voltage • Package: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM7503GS-BK bits : 8 bits : 1.2 kW driving available : Controlled by processor, 8 levels MSM7503 2/41 ...

Page 3

... SW6 F Tone GEN. SW8 1 kHz SW18 S Tone GEN. SW21 Latch SW15 SW11 SW20 VLCD GEN. Man-machine INTF SW19 Scanning Output SG GEN. SGT SGC PO0~PO7 MSM7503 PS SYNC CLK1 CLK2 CLK3 CLC FHW FD FK BHW BD BDS CTEST LRSTN TO AIN CAI SW12 ...

Page 4

... LRSTN SAO 10 VLCD RMO1 14 RMO0 15 RMI 16 SPI 17 SPO 18 RPO 19 R2I 20 R1I 21 MLDYI 22 MPBO 23 24 MPBI 80-Pin Plastic QFP MSM7503 64 CEN 63 RDN 62 WRN 61 AD1 60 AD0 59 DB7 58 DB6 57 DB5 56 DB4 55 DB3 54 DB2 53 DB1 52 DB0 51 PI7 50 PI6 49 PI5 48 PI4 47 PI3 ...

Page 5

... Through processor control, the calling tone volume is selectable from 4 levels and one of six tone combinations is selectable. Initially, the calling tone volume is set at a maximum and the tone combination is set Wamble tone by a combination of 1 kHz and 1.3 kHz. The SA0 outputs pulse waveforms using reference potential. MSM7503 5/41 ...

Page 6

... The typical gain between SPI and SPO is 0 dB. But, the 2-stage gain amplifier allows to set up a gain between 0 dB and – step gain between 0 dB and – step through processor control. The input resistance of SPI is typically 150 kW (it varies by gain setting). RMI RMO0 MSM7503 R2 R1 6/41 ...

Page 7

... The typical gain between MLDYI and SPO is –3 dB. Through processor control, a gain between – – also settable steps. MLDYI is a high impedance input, so insert an about 100 kW bias resistor between MLDYI and SGT. for the load of 20 kW, SPO can not directly drive a speaker. PP MSM7503 7/41 ...

Page 8

... A signal on the MPBO is output via the TO pin through processor control. During the whole system power down mode, MPBO analog ground level. The gain between MPBO and TO is fixed to 0 dB. TPBI SGT MSM7503 8/41 ...

Page 9

... TO signal is great, CAI should be connected via AC-coupling capacitor. At this time, insert an about 100 kW bias resistor between CAI and SGT. CAO is the analog output of CODEC. CAO should be connected to R1I via AC-coupling capacitor. A bias resistor is not required to R1I. During the whole system or CODEC power down mode, CAO is at the SG voltage level. MSM7503 9/41 ...

Page 10

... B bits (eight bits for voice and data), and the DC bit (bit for DC balance) have been transmitted in burst mode at the bit rate of 256 kHz at interval of 125 msec. These signals should be input in the R1N pin and the R2N pin after separating then into the polarity of "+" and "–". MSM7503 10/41 ...

Page 11

... This signal is always output in the power ON mode. CLC Control signal input for phase-inverting the 256 kHz CLK signal which is output form the CLK3 pin. If the reference phase is set by setting CLC to "0", the CLK signal of 256 kHz is phase-inverted against the reference phase by setting CLC to "1". MSM7503 11/41 ...

Page 12

... The signal output of the extracted K bit (8 kbps) from the line receive signals which are input to the R1N and R2N pins. This signal is output synchronizing to the rising edge of a SYNC output signal output pin of an open drain type with a pulled-up resistance of about 10 kW. MSM7503 12/41 ...

Page 13

... CLK oscillator circuit input and output input and X2 is output. A crystal oscillator of 8.192 MHz should be connected between X1 and X2. If the frequency deviation in CLK oscillation is great with respect to the receive data rate, the noise of the CODEC increases. The oscillation frequency deviation in CLK should be kept in 20 ppm or less. MSM7503 13/41 ...

Page 14

... Data on the data bus is written into the registers at the rising edge of WRN under the condition of digital "0" of CEN (Chip Enable). While CEN is in digital "1" state, WRN becomes invalid. The Write cycle is a minimum regardless of the presence or absence of clock signals. MSM7503 Function 14/41 ...

Page 15

... When this input pin is at digital "0" level, the LRSTN output goes to "0" level. When this input pin is at "1" level, the internal WDT does not affect the LSRTN output. CTEST Test pin for shipment testing. This pin should be set to "0" level. MSM7503 15/41 ...

Page 16

... PO0 to PO7 Other digital output pins except PO0 to PO7 25°C ±3°C –50 –50 Condition Min. 20 0.6 — — –10 –50 With respect to SG –25 –100 MSM7503 Rating Unit –0 0 –0 0 -55 to 150 °C Typ. Max. ...

Page 17

... See Fig BHW Input See Fig Input See Fig Input See Fig R1N, R2N See Fig. 5 — See Fig. 5 1.35 — See Fig. 5 — MSM7503 Typ. Max. Unit — — ns — — ns — — ns — — ns — — ns — ...

Page 18

... TPAO, MPAO –100 — TPAI, TPBI, MLDYI, RMI, MPAI, MPBI R1I, R2I, SPI CAI (fin : < 4 kHz) VA/2 — –0.05 FORCE Current SINK Current PI0 to PI7 MSM7503 = 5 V ±5 –10°C to 70°C) DD Typ. Max. Unit — — — ...

Page 19

... LÆH CLK2ÆFD See Fig. 4 HÆL LÆH See Fig. 4 HÆL CLK1, CLK2, CLK3 T1N, T2N "L" Width See Fig. 5 SYNC, CLK1, CLK2 CLK3 When use Xtal MSM7503 = 5 V ±5 –10°C to 70°C) DD Typ. Max. Unit 0.2 — 1.5 ms 0.2 — ...

Page 20

... AIN = SG m — — — — *2 CAI Æ BHW 0.5671 1020 0 FHW Æ CAO 0.5671 CAI Æ CAO 1020 0 BCLOCK = 64 kHz MSM7503 = 5 V ±5 –10°C to 70°C) DD Min. Typ. Max. Unit 20 27 — 0.07 0.20 Reference dB –0.03 0.20 0.06 0.20 0.0 0.38 0.80 –0.03 0.20 ...

Page 21

... FHW Æ BHW CAO left open – 4000 Hz 72 kHz 300 to 0 4.6 kHz to 100 kHz 3400 fa = 470 –4 2fa– 320 50 *4 kHz mV pp MSM7503 = 5 V ±5 –10°C to 70°C) DD Min. Typ. Max. Unit — 0.19 0.75 — 0.12 0.35 — 0.02 0.125 ms — ...

Page 22

... TPAI:Terminated in 510 W Measured at TO TPAO-TPBI Directly — — connected Set at typical gain *5 TPAO, TO, MPAO, MPBO 1020 — MSM7503 = 5 V ±5 –10°C to 70°C) DD Typ. Max. Unit 18.0 20.0 22.0 dB 15.7 17.7 19.7 dB –5.0 –3.0 –1.0 –8.0 –6.0 – ...

Page 23

... Typical gain is set 1020 –4.0 between SPI and SPO MSM7503 ( ±5 –10 to 70°C) DD Min. Typ. Max. Unit –8.0 –6.0 –4.0 dB –8.0 –6.0 –8.0 –6.0 –4.0 – ...

Page 24

... RMO0, RMOB *5 RPO, SPO — — Resister of 1.2 kW between RMO0 and RMO1 1020 — Measurement at each output 1020 –4 Between R1I and TO MSM7503 = 5 V ±5 –10°C to 70°C) DD Typ. Max. Unit –8.0 –6.0 –4.0 –12.0 –10.0 dB –18.0 –16.0 – ...

Page 25

... DB0 — To GND MSM7503 = 5 V ±5 –10°C to 70°C) DD Min. Typ. Max. Unit 63 90 117 84 120 156 mV pp 105 150 195 126 180 234 112 160 208 mV pp 7.5 11 ...

Page 26

... DB0 to DB7 PO0 to PO7 Latch Output td RST2 T WDT td T RST3 WDT t WRST (b) LRSTN output timing by the internal WDT Figure AW2 AR1 t t CW2 CR1 DW1 DW2 t PDDATA t PDSCN t PDLA Figure 2 MSM7503 RST1 t AR2 t CR2 PDDATA 26/41 ...

Page 27

... BHW Input T SBHW D-, K-bit Signal I/O Timing SYNC CLK2        CLK3 (CLC=1) CLK3 (CLC=0) FD Output BD Output FK Output 1/f SYNC T WSYNC 1/f CLK1 HBHW Figure 3 1/f CLK2 1/f CLK3 SBD T HBD td FK Figure 4 MSM7503 td SCK1 SCK2 td SCK3 27/41 ...

Page 28

Ping-Pong Transmission Signal Timing Receive (62.4 ms) Wave Shape of Line Signal R1N Receive TWB R2N TCB Receive Data SYNC CLK1 FHW BHW TB8 CLK2 CLK3 T1N Transmit T2N Transmit Data ...

Page 29

FUNCTIONAL DESCRIPTION Control Data Description Sounder Calling Tone and tone ON/OFF control WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ...

Page 30

Level and frequency control of sounder and R-tone WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 — — — ...

Page 31

PB tone control WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ...

Page 32

SW control and timer reset WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ...

Page 33

Gain setting (receive gain, side tone gain) WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 — ...

Page 34

Gain control (transmit hold tone, PB tone, microphone input, handset input) WRITE Mode Address Data AD1 = 0, AD0 = 1 Control Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 — — ...

Page 35

Gain control (receive PAD, speaker) WRITE Mode Address Data AD1 = 0, AD0 = 1 Control Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 — — 1 ...

Page 36

Key scanning signal output control WRITE Mode Address Data AD1 = 1, AD0 = 0 Controlo Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Output Data Key scanning data read out Read Mode Address Data AD1 = 1, AD0 ...

Page 37

Special functions WRITE Mode Address Data AD1 = 1, AD0 = 1 Contorol Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LCD Deflection Angle Control Voltage Output ...

Page 38

... Semiconductor APPLICATION CIRCUIT Handset MSM7503 Speaker 38/41 ...

Page 39

TPAO TPBI MPAI MPAO VOL 9 TPAI + VOL 8 CAO R1I – VOL 10 R2I RPO RMI – SW5 – SW5 RMO0 0 dB RMO1 – SPO – VOL 5 SW21 – VOL 12 SW20 VOL ...

Page 40

... Connect analog input pins and digital input pins that are not used to the SG pin and to GND, respectively. • When the data is written differently from the data defined in the section, Control Data Description in Functional Description, the device is not guaranteed in normal operation. MSM7503 40/41 ...

Page 41

... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM7503 (Unit : mm) Package material Epoxy resin ...

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