msm7503 Oki Semiconductor, msm7503 Datasheet - Page 15

• Manufacturer Part Number: msm7503
• Description: Multi-function Pcm Codec
• Manufacturer: Oki Semiconductor

¡ Semiconductor
MSM7503
RDN
Read signal input to read PI0 to PI7 out of the processor.
When CEN and RDN are in digital "0" state, the digital values on PI0 to PI7 are output onto the
data buses DB0 to DB7. While CEN is in digital "1" state, the RDN signal becomes invalid.
CEN
Chip Enable signal input.
When CEN is in digital "0" state, WRN and RDN are valid.
VLCD
By processor control, VLCD outputs a DC voltage between 0 and 1.4 V is about 0.2 V step.
This is used to control the deflection angle of the LCD display. VLCD has the internal resistance
value of about 1 kW, so the external load of over 100 kW should be used. During initialized state,
VLCD outputs the voltage of 0 V.
LRSTN
Reset signal output for external circuit.
This reset signal output pin goes to "0" level when the power supply is approximately more than
4.0 V or when the TEST pin is at digital "0" level and the watchdog timer (WDT) outputs a signal.
The WDT output does not affect the LSRTN output when TEST pin is at digital "1" level.
The LRSTN signal is also used as a reset signal for internal registers.
When LRSTN is at "0" level, all internal control registers are initialized.
The internal WDT outputs a 500 ms cycle signal when the LRSTN is at digital "1" and the
processor does not send a timer reset signal.
Refer to the figure 1 for the output timing of this output.
TEST
Control signal input for deciding valid/invalid of reset control from the internal WDT output.
When this input pin is at digital "0" level, the LRSTN output goes to "0" level. When this input
pin is at "1" level, the internal WDT does not affect the LSRTN output.
CTEST
Test pin for shipment testing.
This pin should be set to "0" level.
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