msm7712 Oki Semiconductor, msm7712 Datasheet
msm7712
Related parts for msm7712
msm7712 Summary of contents
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... Wireless LAN Baseband Controller DESCRIPTION The MSM7712 is the first release in a series of wireless LAN baseband controllers, designated .XI (a suffix of the IEEE P802.11 protocol). The MSM7712 integrates the baseband physical layer and the lower MAC layers into a single IC that supports specific draft standards of the P802.11 specification. The architecture targets optimum integration with maximum user flexibility, providing a migration path to low-cost mod- ule handsets and access points ...
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... BLOCK DIAGRAM Figure 1 shows a typical WLAN card. The MSM7712 provides a direct connection to a host interface, pro- cessor, radio, shared memory, and configuration E code ...
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... PACKAGE DRAWING 1.25 TYP 109 1.25 TYP 144 0.17 0.05 0.22 0.05 0.5 108 LQFP144-P-2-2-0.50-K PIN 1 INDEX (Mirror Finish) 1 Seating Plane 0.10 1.0 0.2 0~0.25 0.5 TYP Dimensions in millimeters MSM7712 0. Oki Semiconductor 3 ...
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... MSM7712 ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...
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... The host computer typically runs a NDIS or ODI driver that communicates to the local processor via shared memory and interrupts. The local processor performs the higher layers of the IEEE 802.11 MAC protocol while the MSM7712GS-K performs the lower layers of MAC and the PHY under control of the local processor. ...
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... PCLK Output The processor clock is provided by the MSM7712. From power up PCLK is set at SCK divided register programs PCLK to be from SCK to SCK divided by 8. The PCLK frequency selection allows a processor to op- erate at either low power or maximum performance. Within a 80C186 system, the processor is synchronized to the MSM7712 by monitoring the processor CLKOUT signal and skipping PCLK periods if necessary ...
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... For minimal cost applications local processor code may reside in shared memory. This may affect the processor speed because accesses to shared memory may have wait states inserted. The RAM access time is (1.5 clock cycles less 18 ns). Hence, with a MSM7712 clock (RCLK) of 16MHz, the RAM requires an access time better than 75 ns. ...
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... RCK at 16 MHz). Host Interface (Between Adapter Card and Computer or Laptop) The 16-bit PCMCIA interface is fully supported by the MSM7712 with no additional logic. Access to attribute memory (the CIS configuration data) and I/O memory (host registers) are provided. In normal operation, access to the baseband controller registers and shared buffer memory is via a small number of I/O addresses ...
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... The card reset is provided by HRST. HRST must be asserted for a period of time from power up to allow the oscillator to settle. The MSM7712 is set to a default state while HRST is asserted and SCK is available. From HRST being deasserted the MSM7712 must download the CIS table from the E reset procedure is considered complete ...
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... Clear Channel Assessment is performed). The timing of TXC1 and TXC2 at the start of a transmit is programmable from the deassertion of RXC1. RXC2 is typically used for TX Power Amplifier switching, and its assertion depends on the power control mode selected in the MSM7712. This pin is asserted to power up the radio circuitry (i.e. local oscillators) for reception. The pin is programmable to be open-collector (active low) or open-drain (active high) ...
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... Once a valid receive signal is determined (CCA invalid) the RSSI can be measured with the external comparator/DAC and a SAR within the MSM7712. The RSSI measurement is performed for internal and external modem options when CCA is determined. The same DAC can be used for both TX power control, RSSI threshold and RSSI measurement A clock to the radio is provided on this pin ...
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... When MSEL=1 (low-cost 1 Mbps modem), the RXD pin is used for baseband data input from a radio which has a built-in analog data slicer. The MSM7712 has a clock recovery circuitry to synchronize to the incoming data. The recovered clock is output on a diagnostic pin for test purposes. ...
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... Direction SCK Input The system clock to the MSM7712 is provided by this pin. The clock must always be active (i.e. when reset is asserted). The WLAN card operates synchronously to this clock. The MSM7712 and radio operate at SCK/2. The internal modem operates at SCK (32 MHz). The processor operates from a division of SCK (divide divide by 8) depending on a register (GLOB_CTL, see Programmers Reference) in the MSM7712 ...
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... Gaussian filtering, to translate CP-FSK into G-FSK, in accordance with the IEEE 802.11 specification (SAW filter at 240 MHz IF recommended) Demodulator The MSM7712 features a digital baseband demodulator, requiring an external discriminator. The MSM7712 supports two modes: • 1Mbit/s 2-ary FSK • 2 Mbit/s 4-ary FSK. ...
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... V, CORE DD RST asserted, SCK active PAD DD RST asserted, SCK active CORE DD RST asserted, SCK active PAD DD RST asserted, SCK active MSM7712 Rating Unit -0.3 to 4 +0 +0.3 DD -10 ~ +10 mA -10 ~+10 mA -65 ~ 150 ˚C Range Unit 2 ...
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... AC Characteristics Processor Interface The MSM7712 is designed to operate with the V80C86, V33, V53A, and 80C186 processors. Refer to the appropriate processor data sheets for detailed information. Host Interface The MSM7712 meets the timing requirements of the PCMCIA interface ...
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... TXC2 asserted to IF data output ONT1IF t CSENSE deasserted to TXC2 deasserted OFFCST2 t TXC2 deasserted to TXC1 deasserted OFFT2T1 t TXC1 deasserted to RXC1 asserted OFFT1R Description t t SKI SKH S(DO-SK) H(SK-DO) 2 Figure 7. E PROM Timing Description MSM7712 Min. Typ. Max. Symbol - 2000 - - 2000 - - 2000-125 - Min. Typ. Max. Symbol 0 ...
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... Ts (rk-ifd (ifd-rk RCK t S(RK-IFD) IFD[3:0] Figure 11. IFD[3:0] Bus Timing (MSEL = 2, Receiving) Description Max. Notes (RCK at 16 MHz) - Setup time of IFD[] data to rising clock - Hold time of IFD[] data after rising clock t S(IFD-RK) MSM7712 Min. Typ. Max. Symbol 10 – – ns Oki Semiconductor 19 ...
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... MSM7712 ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...