wm8199scds-v Wolfson Microelectronics plc, wm8199scds-v Datasheet - Page 6

• Manufacturer Part Number: wm8199scds-v
• Description: 20msps 16-bit Ccd Digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8199
ELECTRICAL CHARACTERISTICS
Notes:
1.
2.
w
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T
PARAMETER
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Conversion rate
Full-scale input voltage range
(see Note 1)
Input signal limits (see Note 2)
Full-scale transition error
Zero-scale transition error
Differential non-linearity
Integral non-linearity
Channel to channel gain matching
Total output noise
References
Upper reference voltage
Lower reference voltage
Input return bias voltage
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
RLCDAC resolution
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLC deviation
Offset DAC, Monotonicity Guaranteed
Resolution
Differential non-linearity
Integral non-linearity
Step size
Output voltage
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
SYMBOL
V
V
V
V
V
V
RLCSTEP
RLCSTEP
VRB
VRX
V
RLCBOT
RLCBOT
RLCTOP
RLCTOP
DNL
VRT
DNL
INL
INL
V
RTB
IN
PGA[7:0] = 4B(hex)
PGA[7:0] = 4B(hex)
VRLC = 0 to AVDD
Code FF(hex)
CONDITIONS
Code 00(hex)
Gain = 0dB;
Gain = 0dB;
AVDD=5V
AVDD=5V
AVDD=5V
Max Gain
Max Gain
Min Gain
Min Gain
TEST
A
= 25°C, MCLK = 32MHz unless otherwise stated.
MIN
1.4
16
0
+260
-260
4.08
1.25
2.85
1.35
1.65
0.25
0.17
0.39
0.26
4.14
2.81
0.25
2.02
TYP
0.4
1.5
1.6
0.1
20
20
36
25
50
25
1
5
2
2
4
8
PD, Rev 4.4, July 2008
AVDD
MAX
1.6
0.5
1
1
Production Data
LSB rms
LSB rms
mV/step
V/step
V/step
MSPS
Vp-p
Vp-p
UNIT
LSB
LSB
LSB
LSB
mV
mV
mA
bits
mV
bits
mV
mV
µA
%
Ω
Ω
Ω
V
V
V
V
V
V
V
V
V
6