wm8198scds-v Wolfson Microelectronics plc, wm8198scds-v Datasheet - Page 21
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wm8198scds-v
Manufacturer Part Number
wm8198scds-v
Description
8 + 8 Bit Output 16-bit Cis/ccd Afe/digitiser
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8198SCDS-V.pdf
(33 pages)
WM8198
REFERENCES
POWER SUPPLY
POWER MANAGEMENT
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Figure 19 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins
VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin
VRLC/VBIAS
The WM8198 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)
supplies.
Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit and SELPD bit low. Alternatively, when control bit SELPD is
high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the
user to optimise power dissipation in certain modes, or to define an intermediate standby mode to
allow a quicker recovery into a fully active state. In Line-by-line operation, the green and blue channel
PGAs are automatically powered down.
All the internal registers maintain their previously programmed value in power down modes and the
Control Interface inputs remain active. Table 3 summarises the power down control bit functions.
Table 3 Power Down Control
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
EN
X
0
1
INPUT
PINS
POSNNEG = 0
POSNNEG = 1
SELDPD
0
0
1
MCLK
VSMP
Device completely powers down.
Device completely powers up.
Blocks with respective SELDIS[3:0] bit high are disabled.
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PD, Rev 4.3, August 2008
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Production Data
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