ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 26

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

OKI Semiconductor
• Internal Input System Clock (IICLK)
8-bit 4:2:2 mode
The IICLK is IICLK = ICLK in 16-bit 4:2:2 mode whereas in 8-bit 4:2:2 mode and ITU-R BT.656 mode
it is the clock pulse obtained by internally frequency-dividing ICLK to 1/2.
In 8-bit 4:2:2 mode, the position which is two ICLK clocks delayed from the rise of IHS is used for
resetting and IICLK is generated by frequency-dividing ICLK to 1/2.
Normally reset of IICLK presumes the rise position of positive polarity IHS (IHSINV = 0), but by setting
IHES (SUB:41h-bit[5]) and IHSINV, selection of compliance with negative polarity IHS and fall
position is also possible.
In ITU-R BT 656 mode, ICLK is frequency-divided to 1/2 based on SAV.
In 8-bit 4:2:2 mode, if the phase of IHS for luminance and chrominance data reverses (number of ICLKs
from IICLK reset to initial chrominance data is odd), it is possible to avoid the reversal by setting ICINV
(SUB:41h-bit[4]).
YI[7:0]
Table F1-2-1 (4) Compliance with Luminance-Chrominance Phase Reversal
IICLK
IICLK
Reset
ICLK
IHS
ICINV
IHES
0
1
0
1
0
1
Number of ICLKs from IICLK reset to initial chrominance data is even.
Figure F1-2-1 (2) IICLK Phase Timing Example
Number of ICLKs from IICLK reset to initial chrominance data is odd.
IHSINV
Table F1-2-1 (3) IICLK Reset Position
0
0
1
1
Positive polarity IHS rise (horizontal Sync. signal front
edge)
Positive polarity IHS fall (horizontal Sync. signal rear
edge)
Negative polarity IHS fall (horizontal Sync. signal front
edge)
Negative polarity IHS rise (horizontal Sync. signal rear
edge)
Usage conditions (8-bit 4:2:2 mode)
Reset position
Crn
Yn
Cbn
PEDL87V21071-01
Yn+1
ML87V21071
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