ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 83

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

2.2.4 Memory Control Setting 2 (phase adjustment)
OKI Semiconductor
SUB_ADDRESS = 44h(W/R): Input system memory control vertical phase adjustment setting
SUB_ADDRESS = 45h(W/R): Input system memory control horizontal phase adjustment setting
Register name
Register name
DATA_BIT
DATA_BIT
NPVWE[4:0]
INPR
NPHWE[7:0]
When INSINV = 0, sets the number of lines (IHS input count) from the IVS fall position up to the
vertical standard write start position.
When IVSINV = 1, the number of lines is set from the IVS rise position.
NPVWE[4]is enabled only when INPR = 1.
Sets progressive input.
When IHSINV = 0, sets the number of pixels from the IHS rise position up to the horizontal standard
write start position.
When IHSINV = 1, sets the number of pixels from the IHS fall position.
INPR
BIT7
BIT7
Initial value: 1000; Setting range: 00001 to 11111
Initial value: 0; Setting range: 0 to 1
Initial value: 1000_0000; Setting range: 0000_0001 to 1111_1111
7
(Reserved) (Reserved)
Table R2-2-4 Progressive Input Setting
BIT6
BIT6
INPR
6
0
1
BIT5
BIT5
Progressive input (525p/625p)
5
Interlace (525i/625i)
BIT4
BIT4
NPHWE
Input
4
4
BIT3
BIT3
3
3
NPVWE
BIT2
BIT2
2
2
BIT1
BIT1
1
1
PEDL87V21071-01
ML87V21071
BIT0
BIT0
0
0
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