mt88l89asr1 Zarlink Semiconductor, mt88l89asr1 Datasheet - Page 12

• Manufacturer Part Number: mt88l89asr1
• Description: 3 V Integrated Dtmf Transceiver With Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor

Microprocessor Interface
The MT88L89 design incorporates an adaptive interface, which allows it to be connected to various kinds of
microprocessors. Key functions of this interface include the following:
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•
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Figure 17 shows the timing diagram for the Motorola microcontrollers. The chip select (CS) input is formed by
NANDing address strobe (AS) and address decode output. The MT88L89 examines the state of DS/RD on the
falling edge of CS. For Motorola bus timing DS/RD must be low on the falling edge of CS. Figure 12(a) shows the
connection of the MC68L11/MC68B11 Motorola processor to the MT88L89 DTMF transceiver.
Figures 18 and 19 are the timing diagrams for the Intel 8xL5x series (12 MHz) micro-controllers with multiplexed
address and data buses. The MT88L89 latches in the state of DS/RD on the falling edge of CS. When DS/RD is
high, Intel processor operation is selected. By NANDing the address latch enable (ALE) output with the high-byte
address (P2) decode output, CS can be generated. Figure 12(b) shows the connection of these Intel processors to
the MT88L89 transceiver.
Note: The adaptive micro interface relies on high-to-low transition on CS to recognize the microcontroller interface.
This pin must not be tied permanently low. Only one register access is allowed on any CS assertion.
The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register
contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data
Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is
accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write
operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the
same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-
only status register indicates the current transceiver state (see Table 8).
A software reset must be included at the beginning of all programs to initialize the control registers upon power-up
or power reset (see Figure 15). Refer to Tables 4-7 for bit descriptions of the two control registers.
The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when
the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a
square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external
pull-up resistor (see Figure 13 and Figure 14).
Continuous activity on DS/RD is not necessary to update the internal status registers.
Compatible with Motorola and Intel processors. Determines whether input timing is that of an Intel or
Motorola controller by monitoring
DS/RD, on the CS falling edge.
Differentiates between multiplexed and non-multiplexed microprocessor buses. Address and data are
latched in accordingly.
MC68L11/
MC68B11
AD0-AD3
A8-A15
Figure 12 a) & b) - MT88L89 Interface Connections for Various Intel and Motorola Micros
RW
AS
E
12 (a) Motorola
CS
D0-D3
RS0
DS/RD
R/W/WR
MT88L89
Zarlink Semiconductor Inc.
MT88L89
12
8xL5x
A8-A15
ALE
WR
RD
P0
12 (b) Intel
CS
D0-D3
RS0
DS/RD
R/W/WR
MT88L89
Data Sheet