mt88l89asr1 Zarlink Semiconductor, mt88l89asr1 Datasheet - Page 3

• Manufacturer Part Number: mt88l89asr1
• Description: 3 V Integrated Dtmf Transceiver With Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor

Pin Description
Functional Description
The MT88L89 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain
setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and
pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.
The adaptive micro interface allows various microcontrollers to access the MT88L89 internal registers.
Power-Down
The MT88L89 provides enhanced power-down functionality to facilitate minimization of supply current
consumption. DTMF transmitter and receiver circuit blocks can be independently powered down via register
control. When asserted, RxEN control bit powers down all analog and digital circuitry associated solely with the
DTMF and Call Progress receiver. The TOUT control bit is used to disable the transmitter and put all circuitry
associated only with the DTMF transmitter in power-down mode. With the TOUT control bit is set to zero, the TONE
output pin is held in a high impedance (floating) state. When both transmitter and receiver circuits are powered
down, circuits utilized by both the DTMF transmitter and receiver are also powered down. This power-down control
disables the crystal oscillator, and the V
a high impedance state.
Input Configuration
The input arrangement of the MT88L89 provides a differential-input operational amplifier as well as a bias source
(V
amp output (GS) for gain adjustment.
For applications which are required to meet a guaranteed RX input level of -29 dBm over the full temperature and
supply voltage range, a unity gain input configuration as shown in Figures 3 and 4 can be used.
For applications which require signal detection lower than -29 dBm, the external resistors can be configured to give
adequate gain. For example, if the application requires tone detection of -31 dBm, the input gain can be set to
+2 dB with the external resistors (see Figures 13 and 14 for value of resistors). However, when +2 dB gain is used,
the corresponding maximum input signal level must not exceed -6 dBm.
14-17 18-21 19-22
Ref
20
18
19
20
), which is used to bias the inputs at V
Pin #
8, 9
16,
24
22
23
24
17
23-25
10-11
3, 5,
28
26
27
28
16
D0-D3
Name
St/GT
V
ESt
NC
DD
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or
RD = 1 (Intel). CMOS compatible.
Early Steering output. Presents a logic high once the digital algorithm has
detected a valid tone pair (signal condition). Any momentary loss of signal
condition will cause ESt to return to a logic low.
Steering Input/Guard Time output (bidirectional). A voltage greater than V
detected at St causes the device to register the detected tone pair and update the
output latch. A voltage less than V
The GT output acts to reset the external steering time-constant; its state is a
function of ESt and the voltage on St.
Positive power supply (3 V typ.).
No Connection.
Ref
generator. In addition, the IRQ, TONE output and DATA pins are held in
DD
/2. Provision is made for connection of a feedback resistor to the op-
Zarlink Semiconductor Inc.
MT88L89
3
TSt
Description
frees the device to accept a new tone pair.
Data Sheet
TSt