mt88l89asr1 Zarlink Semiconductor, mt88l89asr1 Datasheet - Page 2

• Manufacturer Part Number: mt88l89asr1
• Description: 3 V Integrated Dtmf Transceiver With Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor

Pin Description
20
10
11
12
13
1
2
3
4
5
6
7
8
9
R/W/WR
OSC1
OSC2
TONE
VRef
VSS
IN+
GS
CS
Pin #
IN-
20 PIN /PLASTIC DIP/SOIC
24
10
12
13
14
15
11
1
2
3
4
5
6
7
10
1
2
3
4
5
6
7
8
9
28
12
13
14
15
17
18
1
2
4
6
7
8
9
DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input
IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this
Name
OSC1
OSC2
TONE
(WR)
R/W
RS0
V
V
GS
IN-
CS
20
19
18
17
16
15
14
13
12
11
IN+
Ref
SS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
Non-inverting op-amp input.
Inverting op-amp input.
Gain Select. Gives access to output of front end differential amplifier for
connection of feedback resistor.
Reference Voltage output (V
Ground (0 V).
Oscillator input. This pin can also be driven directly by an external clock. CMOS
compatible.
Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
Output from internal DTMF transmitter. High impedance when TOUT bit in Control
Register A (CRA) is set to low. Requires resistive termination to V
(Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible.
Chip Select input must be gated externally by either address strobe (AS), valid
memory address (VMA) or address latch enable (ALE) signal, depending on
processor used. See Figure 12. Must not be tied low. CMOS compatible.
Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible.
is only required when the device is being accessed. CMOS compatible.
output goes low when a valid DTMF tone burst has been transmitted or received.
In call progress mode, this pin will output a rectangular signal representative of the
input signal applied at the input op-amp. The input signal must be within the
bandwidth limits of the call progress filter. See Figure 10.
R/W/WR
OSC1
OSC2
TONE
VRef
VSS
IN+
GS
NC
NC
Figure 2 - Pin Connections
IN-
CS
Zarlink Semiconductor Inc.
10
11
12
MT88L89
1
2
3
4
5
6
7
8
9
24 PIN SSOP
2
24
23
22
21
20
19
18
17
16
15
14
13
DD
/2).
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
Description
OSC1
OSC2
VRef
VSS
NC
NC
NC
5
6
7
8
9
10
11
28 PIN PLCC
•
SS
.
Data Sheet
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0