le75183 Zarlink Semiconductor, le75183 Datasheet

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le75183

Manufacturer Part Number
le75183
Description
Line Card Access Switch
Manufacturer
Zarlink Semiconductor
Datasheet

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APPLICATIONS
FEATURES
RELATED LITERATURE
A
NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and
technology of Legerity Holdings.
Central office
DLC
PBX
DAML
HFC/FITL
Small size/surface-mount packaging
Monolithic IC reliability
Low impulse noise
Make-before-break, break-before-make operation
Clean, bounce-free switching
Low, matched ON-resistance
Built-in current limiting, thermal shutdown, and SLIC
protection
5-V only operation, very low power consumption
Battery monitor, all OFF state upon loss of battery
No EMI
Latched logic level inputs, no drive circuitry
Only one external protector required
TTL logic control compatible
Default power up state
081123 Le75282 Dual Intelligent Line Card Access
Switch Data Sheet
081105 Le75181 Ringing Access Switch Data Sheet
080754 Le58QL061/063 QLSLAC Data Sheet
080676 Le5711 Dual SLIC Data Sheet
081047 Le5712 Dual SLIC Data Sheet
Voice Solution
ORDERING INFORMATION
1.
2.
DESCRIPTION
The VoiceEdge™ family VE750 series of Line Card Access
Switches (LCAS), which includes the Le75181, Le75282 and
Le75183 devices, is a family of monolithic solid-state switches
that is designed to provide both power ringing access and test
access on the analog line card. These devices, while not a pin-
for-pin replacement for the traditional electromechanical relay
(EMR) solution, provide the equivalent switching functionality.
The VE750 series of LCAS is meant as a solid-state alternative
to the EMRs.
The Le75183A/B/C/D devices are pin-for-pin compatible with
Legerity’s L7583A/B/C/D devices.
Legerity also offers a range of compatible SLIC devices and
codec/filters that can be used with the VE750 series LCAS for
complete line card solutions that can be used worldwide in
analog line card applications.
Le75183ADSC
Le75183BDSC
Le75183CDSC
Le75183DDSC
LE75183AFQC
Le75183BFQC
Le75183CFQC
Le75183DFQC
Le75183AFSC
Le75183BFSC
Le75183CFSC
Le75183CZFSC
Le75183DFSC
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
Device
20-Pin SOIC (GULL)
28-pin SOIC (GULL)
Line Card Access Switch
Package Type
Document ID# 081105
Rev:
Distribution:
32-Pin QFN
1
C
Public Document
Le75183
VE750 Series
Tube
Tray
Tube
Date:
Version: 2
Packing
Sep 18, 2007
2

Related parts for le75183

le75183 Summary of contents

Page 1

... The VoiceEdge™ family VE750 series of Line Card Access Switches (LCAS), which includes the Le75181, Le75282 and Le75183 devices family of monolithic solid-state switches that is designed to provide both power ringing access and test access on the analog line card. These devices, while not a pin- for-pin replacement for the traditional electromechanical relay (EMR) solution, provide the equivalent switching functionality ...

Page 2

... Loss of Battery Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Impulse Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Protection .15 Integrated SLIC Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Physical Dimensions .22 28-Pin, Plastic SOIC (GULL) (Le75183AESC/BESC/CESC/CZESC/DESC .22 20-Pin, Plastic SOIC (GULL) (Le75183ASC/BSC/CSC/DSC .23 32-Pin QFN (Le75183QC/BEQC/CQC/DQC .24 Revision history .25 Revision .25 Revision .25 Revision .25 2 Zarlink Semiconductor Inc. ...

Page 3

... This makes the Le75183 especially appropriate for remote power applications such as DAML or FOC/FITL or other Telcordia TA 909 applications where power dissipation is particularly critical. A battery voltage is also used by the Le75183, only as a reference for the integrated protection circuit. The Le75183 will enter an all OFF state upon loss of battery. ...

Page 4

... FGND SCR & Trip Circuit SW1 TBAT SW3 SW4 TLINE SW5 SW7 SW8 SW10 SW9 VDD Control Logic TSD DGND Figure 2. Le75183B/D Le75183B/D FGND SW1 TBAT SW3 SW4 TLINE SW5 SW7 SW9 SW10 VDD Control Logic TSD DGND 4 Zarlink Semiconductor Inc. ...

Page 5

... FGND 20 VBAT RTESTin 19 RBAT 18 RLINE 17 TTESTin RRINGING 16 RTESTout TBAT 15 LATCH 14 TLINE INTESTin 13 TRINGING INRING 12 INTESTout 11 TTESTout DGND 5 Zarlink Semiconductor Inc RBAT 23 NC RLINE RRINGING 19 NC RTESTout VBAT ...

Page 6

... HIGH (not recommended) Battery voltage. Used as a reference for protection circuit supply. Exposed pad in QFN package. No internal electrical connection. Not recommended to make any external electrical connection (such as VBAT or ground) to the EPAD. 6 Zarlink Semiconductor Inc. Ω typical pull up. Ω typical pull down. Ω ...

Page 7

... JESD22 Class 1C compliant −40° to 85°C Typ 5 — rises above typically –10 V, the device will enter an all OFF state and BAT 7 Zarlink Semiconductor Inc. Max Unit 110 °C 150 ° 260 ° – ...

Page 8

... ELECTRICAL CHARACTERISTICS Summary of Assumptions Unless otherwise noted, the test conditions are defined by the Le75183 device application circuit shown in with: = − 5.0 V. BAT DD Supply Currents and Power Dissipation Operational State Condition All OFF VDD=5V, VBAT=-48V Power Ringing or VDD=5V, VBAT=-48V ...

Page 9

... ON-resistance Match Per ON-resistance test condition of SW3, SW4 except All Le75183CZESC ON-resistance Match Per ON-resistance test condition of SW3, SW4 Le75183CZESC ON-state Voltage* Iswitch = I (Figure 2, Switch 3) Maximum Differential Voltage (Vmax) ON-state Voltage* Foldback Voltage Breakpoint 1 (V1) (Figure 3, Switch 4) Foldback Voltage Breakpoint 2 (V2) ...

Page 10

... Vswitch (both poles) = ±330 V, Logic inputs = Gnd –40 °C Vswitch (both poles) = ±310 V, Logic inputs = Gnd dV/dt Sensitivity* — *Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production. Test Condition Measure 10 Zarlink Semiconductor Inc. Min Typ Max Unit I — — 1 SWITCH I — ...

Page 11

... Vswitch (both poles) = ±310 V, Logic inputs = Gnd † — dV/dt Sensitivity *This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded. †Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production. Test Condition @ 50 Hz/60 Hz LIMIT 11 Zarlink Semiconductor Inc. Measure Min Typ Max Unit I — — 1 ...

Page 12

... Sensitivity *This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded. †Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production. Test Condition = 0 Test Condition @ 50 Hz/60 Hz LIMIT 12 Zarlink Semiconductor Inc. Measure Min Typ Max I — — 1 SWITCH I — ...

Page 13

... SLIC is capable of supplying current in excess of the holding current, the SCR may be latched on by the SLIC. The probability of this event depends on the characteristics of the given SLIC and of the holding current of the Le75183 device. The SCR hold current distribution is designed to be safely away from the test limit of 80 mA. The higher the distribution, the lower the probability of the latch ...

Page 14

... When using the Le75183A/B/C/D in this mode, forcing TSD to logic 0 will override the INPUT pins and force an all OFF state. Setting TSD to logic 1 will allow switch control via the logic INPUT pins. However, setting TSD to logic 1 will also disable the thermal shutdown mechanism. This is not recommended ...

Page 15

... Using the Le75183 will minimize and possibly eliminate the contribution to the overall system impulse noise that is associated with ringing access switches. Because of this characteristic of the Le75183 device, it may not be necessary to incorporate a zero cross switching scheme. This ultimately depends upon the characteristics of the individual system and is best evaluated at the board level ...

Page 16

... With the above integrated protection features, only one overvoltage secondary protection device on the loop side of the Le75183 is required. The purpose of this device is to limit fault voltages seen by the Le75183 so as not to exceed the breakdown voltage or input-output isolation rating of the device. To minimize stress on the Le75183, use of a foldback- or crowbar-type device is recommended ...

Page 17

... V – – 2 — BAT BAT — — 1.0 — –3 — –5 — — Le75183B/D dc CURRENT-LIMIT BREAK SWITCHES V BAT <1 µ CURRENT LIMIT (OF BREAK SWITCHES) Unit %/° µA V ...

Page 18

... Figure 5. Switch LIM1 2/3 R –V –V –V –1.5 R MAX 1.5 –I LIM2 –I LIM1 Figure 6. Switches 1, 2, and 5 +I –1.5 V 1.5 V – 2 –I 18 Zarlink Semiconductor Inc. CURRENT LIMITING 2 LIM2 MAX 2 ...

Page 19

... Test Return SW5 SW9 SW7 SW1 Test Out Ringing Test In Return SW3 Break SW4 Break SW10 SW2 SW8 Test Out Test In Ringing Access SW6 Ringing Test Ring Generator Battery 19 Zarlink Semiconductor Inc. +V VBAT (Reference) TIP SCR & Trip Circuit Battery Feed RING ...

Page 20

... A parallel in/parallel out data latch is integrated into the Le75183A/B. Operation of the data latch is controlled by the logic level input pin LATCH. The data input to the latch is the INPUT pin of the Le75183A/B, and the output of the data latch is an internal node used for state control. ...

Page 21

... A parallel in/parallel out data latch is integrated into the Le75183C/D. Operation of the data latch is controlled by the logic level input pin LATCH. The data input to the latch is the INPUT pin of the Le75183C/D and the output of the data latch is an internal node used for state control. ...

Page 22

... PHYSICAL DIMENSIONS 28-Pin, Plastic SOIC (GULL) (Le75183AESC/BESC/CESC/CZESC/DESC) Symbol Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. ...

Page 23

... Plastic SOIC (GULL) (Le75183ASC/BSC/CSC/DSC) Symbol Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. Small Outline Package (20 SOIC) ...

Page 24

... QFN (Le75183QC/BEQC/CQC/DQC) 32 LEAD QFN Symbol Min Nom A 0.80 0.90 A2 0.57 REF b 0.18 0.23 D 8.00 BSC D2 5.70 5.80 E 8.00 BSC E2 5.70 5.80 e 0.80 BSC L 0.43 0. 0.00 0.02 A3 0.20 REF aaa 0.20 bbb 0.10 ccc 0.10 Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. ...

Page 25

... REVISION HISTORY Revision • Added new product offering, Le75183CZESC. • Page 10, Table 5 Ring Return Switch DC Current Limit test condition from Vswitch(on)=+/-10V to +/-20V. • Page 5, Pin Descriptions about EPAD, from "internally connected to digital ground" to "no internal electrical connection". Revision • ...

Page 26

... I C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo are trademarks, and Legerity, the Legerity logo and combinations thereof are registered trademarks of Zarlink Semiconductor Inc. All other trademarks and registered trademarks are the property of their respective owners. © 2007 Zarlink Semiconductor Inc. All Rights Reserved. ...

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