le75183 Zarlink Semiconductor, le75183 Datasheet - Page 20

no-image

le75183

Manufacturer Part Number
le75183
Description
Line Card Access Switch
Manufacturer
Zarlink Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
le75183ADSC
Manufacturer:
ZARLINK
Quantity:
494
Part Number:
le75183ADSC
Manufacturer:
LEGERITY
Quantity:
248
Part Number:
le75183ADSC
Manufacturer:
LEGERITY
Quantity:
20 000
Part Number:
le75183ADSCT
Manufacturer:
ZARLINK
Quantity:
494
Part Number:
le75183AESC
Manufacturer:
legerity
Quantity:
149
Part Number:
le75183AESC
Manufacturer:
ALTERA
0
Part Number:
le75183ASC
Manufacturer:
ST
Quantity:
12 264
Part Number:
le75183ASC
Manufacturer:
N/A
Quantity:
20 000
Part Number:
le75183BESC
Manufacturer:
ALTERA
0
Part Number:
le75183BESC
Manufacturer:
LEGERITY
Quantity:
20 000
Part Number:
le75183BFSC
Manufacturer:
LEGERITY
Quantity:
20 000
Part Number:
le75183CDSC
Manufacturer:
ALTERA
0
Part Number:
le75183CDSC
Manufacturer:
LEGERITY
Quantity:
20 000
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Default power up state.
A parallel in/parallel out data latch is integrated into the Le75183A/B. Operation of the data latch is controlled by the logic level
input pin LATCH. The data input to the latch is the INPUT pin of the Le75183A/B, and the output of the data latch is an internal
node used for state control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through
the data latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active—the Le75183A/B will no longer react to changes at the INPUT
control pin. The state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH
input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.
Note that the TSD input is not tied to the data latch. T
via INPUT and LATCH.
Don’t Care
IN
If T
Forcing T
Idle/Talk state.
TESTout state.
TESTin state
Power ringing state.
Ringing generator test state.
Simultaneous TESTout and TESTin state.
All OFF state.
RING
0
0
0
1
1
0
1
1
SD
Table 12. Truth Table for the Le75183A/B Devices
is logic 1, the thermal shutdown mechanism is disabled. If T
SD
Don’t Care
IN
to logic 0 overrides the logic input pins and forces an all OFF state.
TESTin
0
0
1
0
1
1
0
1
Don’t Care
IN
TESTout
0
1
0
0
0
1
1
1
1/Float
1/Float
1/Float
1/Float
1/Float
1/Float
1/Float
1Float
T
0
SD
2
1
1
1
1
1
1
1
1
Zarlink Semiconductor Inc.
SD
Switches
TESTin
is not affected by the LATCH input. T
Off
Off
On
Off
Off
On
Off
Off
Off
20
SD
is floating, the thermal shutdown mechanism is active.
Switches
Break
On
Off
Off
Off
Off
Off
Off
Off
Off
Ring Test
Switches
Off
Off
Off
Off
On
Off
Off
Off
Off
SD
input will override state control
Switches
Ring
Off
Off
Off
On
Off
Off
Off
Off
Off
Switches
TESTout
Off
Off
On
Off
Off
Off
On
Off
Off
9, 10
3
4
5
6
7
8
9
9

Related parts for le75183