92hd71b5x5prgxb3x8 Integrated Device Technology, 92hd71b5x5prgxb3x8 Datasheet - Page 16

• Manufacturer Part Number: 92hd71b5x5prgxb3x8
• Description: Four Channel Hd Audio Codec, Low Power Optimized, 4-ports, 95db Snr
• Manufacturer: Integrated Device Technology

4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
D0-D3
92HD71B5
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
AFG Power
State
ADC0.CnvrtID.Channel = 0
ADC1.CnvrtID.Channel = 2
ADC0.CnvrtID.Channel = 2
ADC1.CnvrtID.Channel = 0
BITCLK
1.4.11.
SDI
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Asserted (Low)
The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.
EAPD
The EAPD pin (pin 47) also supports SPDIF and GPIO functions. The pin defaults to EAPD after
power on reset and will remain in EAPD mode until either GPIO is enabled for pin 47 or the port I/O
is enabled to support SPDIF. The EAPD value is reflected on the EAPD pin; a 1 causes the external
amplifier to power up, and a 0 causes it to power down. When the EAPD value = 1, the EAPD pin
must be placed in a state appropriate to the current power state of the associated Pin Widget even
though the EAPD value may remain 1. The default state of this pin is 0 (driving low) and a Pull-down
prevents the line from floating high when the part is in reset.
0
RESET#
STREAM ID
0
0
Stream ID
Stream ID
1
STREAM TAG
0
Figure 4. Multi-channel timing diagram
Length
Length
GPIO Enable
Data
Data
0
Disabled
Disabled
Disabled
Enabled
Figure 3. Multi-channel capture
DATA LENGTH
1
-
Table 7. EAPD Behavior
1
Left Channel
Left Channel
ADC0
ADC1
0
Output Enable
0
16
Disabled
Disabled
Enabled
ADC0
L23
-
-
Right Channel
Right Channel
LEFT
ADC0
ADC1
ADC0
L0
ADC0
ADC0
R23
EAPD Power
RIGHT
D2-D3
D0-D1
State
Left Channel
Left Channel
DATA BLOCK
-
-
-
ADC0
R0
ADC1
ADC0
ADC1
92HD71B5
L23
LEFT
output (internal pull-down enabled)
Active - Pin drives the value of the
Hi-Z (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
Active - Pin Drives SPDIFOut0/1
retained until the rising edge of
otherwise the previous state is
ADC1
configuration (internal pull-up
Right Channel
Right Channel
EAPD bit (internal pull-down
immediately after power on,
L0
Active - Pin reflects GPIO0
ADC1
ADC1
ADC0
ADC1
R23
Pin Behavior
RIGHT
RESET#
enabled)
enabled)
ADC1
R0
Null PAD
Null PAD
PC AUDIO
V 1.0, 01/08