mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet - Page 21

• Manufacturer Part Number: mt8986al1
• Description: Multiple Rate Digital Switch
• Manufacturer: Zarlink Semiconductor

x=Don’t care
Applications
Switch Matrix Architectures
The MT8986 is an ideal device for designs of medium size switch matrix. For applications where voice and grouped
data channels are transported within the same frame, the voice samples have to be time interchanged with a
minimum delay while maintaining the integrity of grouped data. To guarantee the integrity of grouped data during
switching and to provide a minimum delay for voice connections, the MT8986 provides the per-channel selection
between variable and constant throughput delay. This can be selected by the V/C bit of the Connection Memory
High locations.
Different connectivities at different data rates can be built to accommodate Non-Blocking matrices of up to 512
channels while maintaining the per channel selection of the device's throughput delay. Some examples of such
Non-Blocking configurations are given in Figures 9 to 11.
For applications where voice and data samples are encoded into individual 64 kb/s time-slots on an 8 kHz frame
basis, the switch matrix can operate with time interchange procedures where only variable throughput delay is
guaranteed. For such applications, the MT8986 device allows cost effective implementations of Non-Blocking
matrices ranging up to 1024 channels. Figures 12 and 13 show the block diagram of implementations with Non-
Blocking capacities of 512 and 1024-channel, respectively.
If frame input offset operation is not required, this register should be cleared by the CPU during system initialization.
BIT
7-5
OFB2-0
NAME
Offset Bits 2-0. These three bits define the time it takes the Serial Interface receiver to recognize
and store the first bit of the serial input streams; i.e., to start assuming a new internal frame. The
input frame offset can be selected to be up to 4 CK clock periods from the time when frame pulse
input signal is applied to the FR input.
OFB2
7
Frame Input Offset Register - Read/Write
Figure 8 - Frame Input Offset (FIO) Register
OFB2
OFB1
0
0
0
0
1
1
1
1
6
OFB0
5
Zarlink Semiconductor Inc.
OFB1
0
0
1
1
0
0
1
1
MT8986
4
X
21
OFB0
X
3
DESCRIPTION
0
1
0
1
0
1
0
1
2
X
Number of Clock Periods
Normal Operation. No bit offsetting.
Reserved
Reserved
Reserved
1
X
1
2
3
4
X
0
Data Sheet