mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet - Page 5

• Manufacturer Part Number: mt8986al1
• Description: Multiple Rate Digital Switch
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Device Overview
With the integration of voice, video and data services in the same network, there has been an increasing demand
for systems which ensure that data at N x 64 kbit/s rates maintain sequence integrity while being transported
through time-slot interchange circuits. This requirement demands time-slot interchange devices which perform
switching with constant throughput delay for wideband data applications while guaranteeing minimum delay for
voice channels.
The MT8986 device meets the above requirement and allows existing systems based on the MT8980D to be easily
upgraded to maintain the data integrity when wideband data is transported. The device is designed to switch 32, 64
or N x 64 kbit/s data. The MT8986 can provide frame integrity for data applications and minimum throughput
switching delay for voice applications on a per channel basis.
The serial streams of the MT8986 device can operate at 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125 µs
wide frames which contain 32, 64 and 128 channels, respectively. In addition, a built-in rate conversion circuit
allows the user to interconnect various backplane speeds like 2.048 or 4.096 or 8.192 Mb/s while maintaining the
control of throughput delay function on a per-channel basis.
By using Zarlink Message mode capability, the microprocessor can access input and output time-slots on a per
channel basis to control external circuits or other ST-BUS devices. The MT8986 automatically identifies the polarity
DIP
40
40
-
-
-
-
PLCC
Pin #
18
28
40
44
6
1
QFP
39
44
12
22
34
44
AS/ALE Address Strobe or Latch Enable (Input). This input is only used if multiplexed
STi15/
STi14/
Name
CSTo
STo9
STo8
IM
Control ST-BUS Output (Output). This is a 2.048 Mb/s output containing 256
bits per frame. The level of each bit is determined by the CSTo bit in the Connect
Memory high locations.
bus is selected via the IM input pin (44 pin only).
The falling edge of this signal is used to sample the address into the address
latch circuit. In case of non-multiplexed bus, this input is not required and should
be left open.
CPU Interface Mode (Input). If HIGH, this input configures MT8986 in
multiplexed microprocessor bus mode. If this input pin is not connected or
grounded, the MT8986 assumes non-multiplexed CPU interface.
ST-BUS Input 15 / ST-BUS Output 9 (Input/three-state output). This pin is only
used if multiplexed CPU bus is selected. If 16-input x 8-output switching
configuration is enabled in the SCB bits (IMS register), this pin is an input
receiving serial ST-BUS stream 15 at a data rate of 2.048 Mbit/s.
If Stream Pair Selection capability is enabled (see switching configuration
section), this pin is the ST-BUS stream 9 output.
When non-multiplexed bus structure is used, this pin should be left open.
ST-BUS Input 14 / ST-BUS Output 8 (Input/three-state output). This pin is only
used if multiplexed CPU bus is selected. If 16-input x 8-output switching
configuration is enabled in the SCB bits (IMS register), this pin is an input that
receives serial ST-BUS stream 14 at a data rate of 2.048 Mbit/s.
If Stream Pair Selection capability is enabled (see switching configuration
section), this pin is the ST-BUS stream 8 output.
When non-multiplexed bus structure is used, this pin should be left open.
Zarlink Semiconductor Inc.
MT8986
5
Description
Data Sheet